Embedded FPGAs start to take hold in SoC

By Chris Edwards |  No Comments  |  Posted: July 16, 2018
Topics/Categories: Blog - EDA, IP  |  Tags: , , ,  | Organizations: ,

The embedded field-programmable gate array (eFPGA) is beginning to find a market, with communications leading the way but machine learning likely to drive broader adoption.

The eFPGA has had a checkered history since the concept first appeared in the 1990s as concerns grew over the cost of mask sets for processes as they approached the 180nm process node. But several attempts to kickstart technology ran into issues of cost and density. The need to maintain programmability, particularly in the interconnect, meant many SoC designers opted for other ways to incorporate flexibility in their products.

The market seems to be changing as users look beyond die cost to the need to support fast-moving standards and novel algorithms that, in some cases, mutate from month to month. Moore’s Law might have slowed down considerably for silicon but a similar exponential has emerged in machine learning, with the number of papers on deep-learning and associated algorithms appearing on the academic site ArXiV more than doubling every two years, according to a presentation by Jeff Dean of Google at the ScaledML conference earlier in the year.

Reaction to slowdown

The slowdown in Moore’s Law and the increase in interest in eFPGAs has a connection. With clock speeds having stalled at around 3GHz for close to 15 years and now processor density being limited by power and cost/performance tradeoffs, attention is shifting in new markets such as machine learning to custom acceleration. Designers have the option to hardwire them, build microcode-programmable custom designs, introduce eFPGA cores to allow the accelerators to mutate as algorithms change, or do all three.

Steve Mensor, vice president of marketing at Achronix, says the company has changed its branding to present itself as a “data acceleration” company in recognition of the shift in attitudes. Rather than focus on the cost savings of not having to deal with mask changes if a design needs to change, Mensor says acceleration looks to be a more convincing pitch for a variety of markets that include machine learning. The current major market for Achronix is in 5G communications, where a focus on low latency makes software processing impractical but also where standards remain fluid.

Flex Logic has also seen adoption in wireless basestations. “Historically, it’s been one of the few high-volume applications for [discrete] FPGAs. But they have problems: they can’t get data in and out of the FPGA fast enough. They also have the issue of the protocols becoming more complicated and being implemented in phases. [With eFPGA] they can tweak things if they make mistakes and still get to market quickly,” says Flex Logic CEO Geoff Tate.

Beyond communications

A key set of early adopters for Flex Logic is in the military and aerospace sector. The company has a deal with Sandia Labs to put the eFPGA cores into radiation-hardened logic. The other key market for Flex Logic at the moment is networking and communications, particularly for switching and interface cards for data-center servers.

As well as 5G, Mensor says cryptocurrency mining has appeared as a key market for Achronix, at least in the short term. Longer term, Mensor sees the data-center storage sector as being important as more processing gets pushed out into the peripherals, particularly as new architectures develop around the new generation of persistent, “storage class” memories such as phase-change RAM, resistive RAM, and the Intel/Micron 3D Xpoint.

Mensor says the revenue is starting to flow for eFPGA design wins: “A year ago we announced we were going to a hundred million dollars in revenue. Eighty per cent of that is discrete; the other 20 per cent of that is embedded-FPGA technology. We have multiple customers and a number of them have gone full cycle, through device bringup, full stress testing and shipped to end customers.

“The interesting the about this is that, of the design wins we’ve got [and taped out], every single one has already repeated,” Mensor claims.

Tate says customers often take the adoption of eFPGA step by step. “Architecturally, when they first use us, they take a baby step: something simple with high confidence it will work. Then they do some more and then some more,” he says, pointing to aerospace as a key sector for Flex Logic where this has been a common pattern.

Learning opportunity

The longer-term opportunity is in machine learning, another sector where fluid algorithms, a lack of standards, and need for processing speed have come together in a way that may drive customers to adopt eFPGA, possibly alongside more coarse-grain reprogrammable architectures. Mensor says the engagements with machine-learning customers tend to be strategic: “All the conversations involve CEOs. The use is more integral and architectural with applications that are very heavy in machine-learning functionality.”

Both Achronix and Flex Logic have developed arithmetic blocks that are tuned for the kind of processing used in today’s deep-learning pipelines, primarily focusing on 8bit multiply-adds. They expect more variants to appear as algorithms needs become clearer. “We expect that customers who engage will tell us ‘here’s what we really want to do’,” Tate says.

At the implementation level Achronix and Flex Logic have taken different paths. Achronix favors tuning its fabric for a small number of processes, such as TSMC’s 16nm FF+. “There are two modes of integration. One has registers around the outside and one with lower latency where you need to share timing information [during signoff],” says Mensor.

Flex Logic has favored an approach that uses the foundry standard cells, with a small number of customized cells, to allow easier porting to a variety of processes. These include the 180nm rad-hard process from Sandia and the upcoming 7nm foundry processes that Tate expects networking and communications customers to adopt. “We end up twice the size of the Achronix in terms of the cell size but our cofounder came up with a more efficient interconnect and we end up using fewer metal layers and still achieve utilization of 90 per cent or more,” Tate claims.

Leave a Comment


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors