The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
How staging virtual prototype bring-up can accelerate the development of embedded software in complex systems.
This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
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