Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust
Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
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