How to combine a display processing unit from one company and a MIPI Display Serial Interface solution from another to build 4K embedded displays for smartphones and AR/VR devices.
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
High-performance vision-processing algorithms need optimized CNN engines to deliver the right performance within the power budget of embedded applications.
Using specialised processors to implement key AI computation tasks such as CNNs.
Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust
Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
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