How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

By Vijay Chobisa |  No Comments  |  Posted: June 11, 2018
Topics/Categories: Embedded - Integration & Debug, EDA - Verification  |  Tags: , , , , ,  | Organizations: ,

Jay Jahangiri, Product Manager for Mentor, a Siemens BusinessVijay Chobisa is the Product Marketing Manager for the Emulation Division at Mentor, a Siemens business, and has more than 15 years experience in the field. Vijay holds a bachelor’s degree of electronics and communication engineering from Jai Narayan Vyas University, Rajasthan, India.

System design companies are increasingly turning to emulators as the only verification platform with the capacity and performance to validate that their system-on-chip (SoC) and system-of-systems (SoS) designs function as intended. On an emulator, this complex SoC and SoS verification happens with the help of an advanced capability called transaction-based co-modeling.

It wasn’t always this way. It wasn’t until the predominant emulation use-model began evolving from in-circuit emulation (ICE) to virtual emulation that it became necessary to use co-modeling technology to perform HW/SW co-verification and debug while maintaining high emulation performance.

Transaction based co-modeling article - block-level diagram

Figure 1. A typical solution block-level diagram (Mentor)

For today’s emulators to be viable, they must have wide solutions support, fast throughput, and advanced co-modeling capabilities to meet new and emerging application demands for complex designs.

Thus, demand for co-model channel versatility and performance has increased as new virtual applications and test platforms emerged for new emulation targets.

Understanding co-modeling technology, its impact on verification and validation, and how best to make trade-offs should be a critical aim for anyone selecting and deploying emulation co-modeling resources. Let’s look at how emulation co-modeling is architected to meet the needs of advanced verification and validation across a wide range of vertical solutions. Those solutions include networking, storage, multimedia, mobile, automotive, wireless, and cellular.

Co-modeling is an untimed, transaction-level interface to the emulator expressed as function calls defined by the Accellera Standard Co-Emulation Modeling Interface (SCE-MI). Co-modeling supports dynamic design configuration, waveform and debug/analysis data streaming and conveying IO data from virtual devices and transactors to and from the design/testbench during emulation. Co-modeling also enhances a wide range of significant test capabilities in the areas of functionality, performance, debug, power-performance analysis, design-for-test (DFT), safety and security of designs, coverage closure, software co-verification and system interoperability.

The co-model channels for Mentor’s Veloce emulator are high-speed, low latency, high-bandwidth channels that follow the same producer-consumer models employed by any IO subsystem in a computer architecture – but with one major difference. Unlike most IO designs, co-model channels are not highly tuned at the expense of other traffic types. For example, a streaming interface and a message-based interface have very different requirements for throughput and latency tradeoffs. In fact, they can work against each other depending on the protocol. Therefore, an architecture that is flexible and tunable to each vertical market requirement should be deployed to meet the wide and demanding array of IO requirements.

More on co-modeling

For more information about transaction-based co-modeling and other attributes of a high-performance emulation platform, download The Veloce Strato Platform: Unique Core Components Create High-Value Advantages.

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