Verification

June 1, 2005

The ultimate wish-list

If you want to get a clear idea of just what is taxing engineers at any given time, you can do a lot worse than following the trends that emerge before each annual Design Automation Conference (DAC). “And this year, it is pretty clear that there are three things on everyone’s mind: power, system-level design […]

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June 1, 2005

SystemVerilog is changing everything

Considering how complexity has grown over the last 20 years, it is amazing how few dramatic shifts in the design and verification methodology have occurred. When they do happen — mylar to layout tools, gates to RTL, hand-crafted test vectors to testbench automation — they make our work as engineers easier and enable us to […]

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