January 4, 2016
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
October 6, 2014
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
March 27, 2014
Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.