Timing analysis shifts to statistical
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
AOCV
ARM, TSMC design explores 16nm finFET issues
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
Achieving multi-scenario signoff quickly and predictably using timing-driven ECO
Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
On-chip variation (OCV)
Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
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