Imec cleans up process for 2µm-pitch 3DIC stacks

Imec is presenting at this weel’s IEEE Electronic Components and Technology Conference (ECTC) a die-to-wafer bonding process that can reduce the bond-pad pitch to 2µm with an overlay error of less than 350nm.

The research institute sees the technique as key to delivering fine-grained die-to-wafer interconnects logic and memory stacks. On the longer term, die-to-wafer bonding will enable also die- and wafer-level optical interconnects, for which Imec is demonstrating a proof of concept.

To deliver the current pitch, and ability to scale to 1µm, Imec found a way to preserve ultraclean surfaces during processing, which includes chemical-mechanical polishing, die singulation and pick-and-place, while maintaining a high throughput. To avoid creating particles during die singulation, the researchers employed a dicing process that uses plasma rather than physical saws.

R&D vice president Eric Beyne said, “In terms of interconnect pitch, die-to-wafer hybrid bonding can now bridge the gap between solder-based die-to-wafer bonding, which is likely to stagnate at 10 to 5µm bump pitch, and wafer-to-wafer hybrid bonding.

“Compared to the latter, die-to-wafer bonding offers the advantage of stacking only known-good dies [for improved yield] and of bonding dies of unequal size,” he added. “Improvements to our process flow will further push the interconnect pitch towards 1µm.”