EDA Topics

December 1, 2009

The A word

According to the International Monetary Fund’s (IMF) latest World Economic Outlook, the possibility of a ‘double-dip’ recession cannot yet be discounted even if current data show the world economy beginning to recover. The IMF’s main concern is that private demand (including consumer spending) is not showing enough strength to restore consistent global GDP growth by […]

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December 1, 2009

Part 4- Power management in OCP-IP 3.0

According to Moore’s Law, system-on-chips (SoCs) should continually become more complex and integrate more components, enabled by each reduction in silicon technologies. However, power consumption does not follow the linear path implied here due to increasing leakage in deep sub-micron technologies. Hence, new power management techniques are needed to reduce power dissipation as much as […]

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December 1, 2009

Interoperable PDKs accelerate analog EDA innovation

Process design kit (PDK) standards are one area that could greatly help reduce the disproportionate time and effort required to realize the analog portion of a design. PDKs have existed for two decades and provide access to foundry-verified data files for such AMS design elements as parameterized layout cells (PCells). However, most have been constructed […]

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December 1, 2009

Overcoming the limitations of data introspection for SystemC

The verification, test and debug of SystemC models can be undertaken at an early stage in the design process. To support these techniques, the SystemC Verification Library uses a concept called data introspection. It lets a library routine extract information from SystemC compound types, or a user-specified composite that is derived from a SystemC type. […]

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December 1, 2009

Silicon test moves up the food chain

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]

September 2, 2009

Part 3 – A unified, scalable SystemVerilog approach to chip and subsystem verification

The article describes LSI’s work on the use of a single SystemVerilog-based (SV) verification environment for both the chip and its submodules. The environment is based on SV’s Advanced Verification Methodology (AVM) libraries, although alternatives are available. One particular reason for choosing AVM was that LSI wanted to leverage its transaction-level modeling capabilities as well […]

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September 1, 2009

Reading the runes

When we first reviewed the consumer electronics market at the beginning of the year, there were still hopes that growth could remain statistically flat despite global economic woes. However, at the beginning of the summer, the Consumer Electronics Association revised its forecast down from January’s -0.7% to -7.7%, implying total factory-gate sales of $165B. The […]

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September 1, 2009

System level DFM at 22nm

The article provides an overview of one common theme in the papers presented at a special session of the 2009 Design Automation Conference, Dawn of the 22nm Design Era. As such, we would recommend that readers wishing to access still more detail on this topic (in particular, on device structures for 22nm and project management […]

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September 1, 2009

Extending UPF for incremental growth

Erich Marschner Accellera’s Unified Power Format (UPF) is in production use today, delivering the low-power system-on-chip (SoC) designs that are so much in demand. Building upon that success, IEEE Std 1801-2009 [UPF] offers additional features that address the challenges of low-power design and verification. These include more abstract specifications for power supplies, power states, and […]

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September 1, 2009

Bringing a coherent system-level design flow to AMS

For two decades, the benefits of ESL and abstractions have been supposedly confined to engineers working on digital designs and to system architects. Analog and mixed-signal (AMS) design has largely remained a ‘circuit level’ activity. This article shows that tools exist that now also allow AMS engineers to exploit abstraction, and that can make all […]

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