At the sharp end

By Paul Dempsey |  No Comments  |  Posted: June 1, 2009
Topics/Categories: EDA - IC Implementation  |  Tags:

The Design Automation Conference (DAC) returns to San Francisco’s Moscone Center, July 26th-31st, and it is hoped that its proximity to Silicon Valley will see attendances hold up well even in tough times.

However, the organizers are looking to more than just geography to guarantee continued interest in chip design’s main annual gathering. This 46th edition of DAC will also see the return of the CEO panel featuring Lip-Bu Tan of Cadence Design Systems, Wally Rhines of Mentor Graphics, and Aart de Geus of Synopsys. There will also be keynotes from technologists such as William Dally of graphics powerhouse Nvidia, and Fu-Chieh Hsu of leading foundry TSMC. And there will be 29 panels spread across the main conference and the Pavillion on the exhibition floor, including one that will have been voted into being by attendees (its topic was still to be determined as the magazine went to press).

Add DAC’s typically strong technical program and you are already at the point where the conference appears to offer something for everyone. Or, actually, does it? One feature being launched this year has been explicitly designed to meet a need that both users and vendors have wanted the conference to address in more detail: the User Track.

The new feature has been put together by Leon Stok, director of EDA for the IBM Systems and Technology Group, and Soha Hassoun, associate professor in the Computer Science Department of Tufts University.

Stok explains the objective, “There is a strong desire among engineers to get their hands on more information about tools, flows and their use to solve the problems they face every day. But at DAC, the main parts of the technical program have tended to be more academic and focused on research. Meanwhile on the floor, the vendors are advertising their tools in a very specific way. What was missing was something in the middle. That is the void we are trying to fill.”

The idea is not entirely new. DAC’s equivalent across the Atlantic, Design Automation and Test in Europe, has also recently launched a track dedicated to industrial case studies and methodologies in everyday use. The initiative proved popular there, and, based on the response from potential contributors, the same looks likely to happen in the USA.

“We have had 117 submissions, and we expected only 50 to 70 in the first year, so it’s gone a lot further than expectations,” says Hassoun. From that, the track has been divided ultimately into 16 front-end presentations (overseen by Hassoun) and 26 back-end presentations (overseen by Stok), plus a packed poster session (see box opposite and on p. 10).

Of course, some may say that DAC is merely duplicating what the major vendors achieve via their user group meetings. These have also long been based around practical case studies and the so-called ‘war stories’ of how tool users overcame a particular design challenge. At a time when some EDA players have been pushing more investment into these events, you might even suggest that DAC’s User Track would be the source of some tension.

“That’s just not the case, though,” says Stok. “The vendors also want there to be a forum at DAC for the exchange of very practical design information in a technical setting that is decoupled from the marketing message.”

Indeed, evidence of that comes in the form of the User Track’s sponsor, Cadence, the vendor with perhaps the greatest reputation prior to this DAC for wanting to ‘go it alone’.

Hassoun also says that DAC’s User Track can fill another
vacuum that single-vendor shows cannot. “The vendor meetings are useful but also, by definition, more focused. And they don’t offer the chance to compare, whereas we have papers from designers working across various flows and with combinations of tools from different sources. It isn’t always the case that you will take everything from one supplier. And again, we have found a number of submissions where the vendor encouraged the user to write the paper up.”

There are also some general trends emerging. At the front-end, Hassoun sees part of the function as bridging the gap between the stronger adoption of ESL strategies seen in Europe and Japan and the more traditional design strategies that are now beginning to move in the same direction in North America. To that end, she is also involved in a workshop of the fast-developing ESL concept of virtual platforms that takes place on Wednesday at this year’s DAC (Room 301).

Among back-end issues, Stok says that timing analysis and dealing with variability are big issues for users, and that parametric yield is also gaining increasing traction. “Also there is a big drive in enabling DFM to try to make appropriate timing and electrical information available to design teams so that they react as early as possible.”

The goals are clear. Get people to show up. Get them talking about the User Track. And have them leave DAC with the sense that they have pulled in a lot of useful information for day-to-day use.

The last point Hassoun and Stok make is that this first run will not be perfect—they never are. By taking this step, DAC begins a process of refinement that will only work if attendees offer detailed feedback about both the good and the bad.

“We’re looking at all the ways we can do that. Some may be formal, some not. There is an ice cream social and we hope to meet a lot of people there. But we’ll be around all week—and we need people to come up to us and tell us what they think,” says Stok.

Design Automation Conference 2009

User Track Program

The User Track runs from Tuesday, July 28 until Thursday, July 30. All the main sessions take place in Room 132 at the Moscone Center.

There is also a separate Poster Session on Wednesday, July 29 from 1.30pm-3.00pm in the Concourse Area.

All details were correct as EDA Tech Forum went to press, but, as ever, may be subject to late change or cancellation. For the most accurate version of the agenda for this and all other DAC events, check the website,

Tuesday, July 28

10.30am-12.00pm Robust Design and Test
  • 1.1 Electromagnetic Interference Reduction on an Automotive Microcontroller, STMicroelectronics
  • 1.2s Power Integrity Sign-Off Flow Using CoolTime and PrimeTime-SI—Flow and Validation, Aptina Imaging
  • 1.3s Improving Parametric Yield in DSM ASIC/SOC Design, Samsung
  • 1.4 Low-Power Test Methodology, STMicroelectronics
2.00pm-4.00pm Practical Physical Design
  • 2.1 Automated Pseudo-Flat Design Methodology for Register Arrays, Intel
  • 2.2 Qualcomm DSP Semi-Custom Design Flow: Leveraging Place and Route Tools in Custom Circuit Design, Qualcomm
  • 2.3s Auto ECO Flow Development for Functional ECO Using Efficient Error Rectification Method Based on Conformal, Intel
  • 2.4s Monte Carlo Techniques for Physical Synthesis Design Convergence Exploration, Intel
  • 2.5s Tortoise: Chip Integration Solution, STMicroelectronics
  • 2.6s ASIC Clock Distribution Design Challenges, Intel
4.30pm-6.30pm Verification: A Front-End Perspective
  • 3.1 Interactive 2-D Projection Cross Coverage Viewer for Coverage Hole Analysis, ClueLogic, Verifore
  • 3.2 Verification of Power Management Protocols Through Abstract Functional Modeling, Intel, Ipflex
  • 3.3 Design Flow for Embedded System Device Driver Development and Verification, Cadence Design Systems, Virtutech

Wednesday, July 29th

9.00am-11.00am Timing Analysis in the Real World
  • 4.1 Design of a Single-Event Effect Fault Tolerant Micro-Processor for Space Using Commercial EDA Tools, European Space Agency, Atmel
  • 4.2 SSTA and Its Application to SPARC 64 Processor Design, Fujitsu
  • 4.3s A Hierarchical Transistor and Gate-Level Statistical Timing Flow for Micro-Processor Designs, IBM
  • 4.4s Unifying Transistor- and Gate-Level Timing Through the Use of Abstraction, IBM
  • 4.5s The Automatic Generation of Merged-Mode Design Constraints, Texas Instruments, FishTail Design Automation
  • 4.6s Modeling Clock Network Variation in Timing Verification, Sun Microsystems
1.30pm-3.00pm Poster Session and Ice Cream Social
3.00pm-4.00pm Toward Front-End Design Productivity
  • 6.1 Unified Chip/Package/Board Codesign Flow for Laminate, Leadframe, and Wafer-Level Packages in a Distributed Design Environment, Infineon Technologies, Cadence Design Systems, CISC Semiconductor Design+Consulting
  • 6.2s Fast FPGA Resource Estimation, Xilinx
  • 6.3s Assessing Design Feasibility Early with Atrenta’s 1Team-Implement SOC, STMicroelectronics, Atrenta
4.30pm-6.00pm Front-End Development: Embedded Software and Design Exploration
  • 7.1s Applying Use Cases to Microcontroller Code Development, Cypress Semiconductor
  • 7.2s Mapping the AVS Video Decoder on a Heterogeneous Dual-Core SIMD Processor, University of Thessaly
  • 7.3s An ‘Algorithm to Silicon’ ESL Design Methodology, STMicroelectronics
  • 7.4s Necessary but Not Sufficient: Lessons and Experiences with High-Level Synthesis Tools, Texas Instruments
  • 7.5 Switching Mechanism in Mixed TLM-2.0 LT/AT System, Intel

Thursday, July 30

9.00am-11.00am Power Analysis and IP Reuse
  • 8.1 Dynamic Power Analysis for Custom Macros Using ESP-CV, Qualcomm
  • 8.2 Power Supply and Substrate Noise Analysis; Reference Tool Experience with Silicon Validation, Kobe University, ARTEC, STARC, Apache Design Solutions
  • 8.3s Modeling and Design Challenges for Multicore Power Supply Noise Analysis, IBM
  • 8.4s Dynamic Power Noise Analysis Method for Memory Designs, Samsung
  • 8.5s Hard IP Reuse in Multiple Metal Systems SOCs, Texas Instruments, Freescale Semiconductor
  • 8.6s Apache Redhawk di/dt Mitigation Method in Power Delivery Design and Analysis, Intel
2.00pm-4.00pm Front-End Power Planning and Analysis
  • 9.1 Power Library Pre-Characterization Automation, NEC, NEC HCL ST
  • 9.2s Chip – Package – PC Board Codesign: Applying a Chip Power Model in System Power Integrity Analysis, Cisco Systems
  • 9.3s New SOC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs, Texas Instruments, Atrenta
  • 9.4 PETRA: A Framework for System-Level Dynamic Thermal and Power Management Exploration, Intel
  • 9.5 ALPES: Architectural-Level Power Planning and Estimation, STMicroelectronics, ST-NXP Wireless, ST-Ericsson
4.30pm-6.00pm Advances in Analog and Mixed-Signal Design
  • 10.1 A Schematic Symbol Library for Collaborative Analog Circuit Development Across Multiple Process Technologies, Stanford University, NetLogic Microsystems, Rambus
  • 10.2 A Mixed-Signal/MEMS CMOS Codesign Flow with MEMS-IP Publishing/Integration, National Chaio Tung University
  • 10.3s Substrate Noise Isolation Characterization in 90nm CMOS Technology, Magwel, NXP Semiconductors
  • 10.4s An Integrated Physical-Electrical Design Verification Flow, Mentor Graphics, SySDSoft


The papers below will be presented at a poster session and ice cream social that will supplement the main User Track sessions, from 1.30pm-3.00pm on Wednesday, July 29. The event will be held on the Concourse Level of the Moscone Center.

The track’s organizers are also encouraging DAC delegates to attend the social to provide feedback on this new section of the conference program. However, if you are unable to attend this or cannot otherwise contact Leon Stok and Soha Hassoun during the conference, you can also email Soha at

User Track – Front End

  • 3-D Visualization of Integrated Circuits in the Electric VLSI Design System, Sun Microsystems
  • Automatic Generation, Execution and Performance Monitoring of a Family of Multiprocessors on Large Scale Emulator, ENSTA, EVE
  • C-Based Hardware Design Using AutoPilot Synthesizing MPEG-4 Decoder onto Xilinx FPGA, University of California – Los Angeles, AutoESL Design Tech
  • C-Based High-Level Synthesis of a Signal Processing Unit Using Mentor Graphics Catapult C, University of Tübingen, Robert Bosch
  • Design and Verification Challenges of ODC-Based Clock Gating, PwrLite
  • Effective Debugging Chip-Multiprocessor Design in Acceleration and Emulation, Chinese Academy
  • Enabling IP Quality Closure at STMicroelectronics with VIP Lane, STMicroelectronics, Satin IP Technologies
  • Formal Verification Based Automated Approaches to System-On-Chip DFT Logic Verification, Texas Instruments
  • Interactive Code Optimization for Dynamically Reconfigurable Architecture, Toshiba
  • Power Gated Design Optimization and Analysis with Silicon Correlation Results, Intel
  • SystemC: A Complete Digital System Modeling Language: A Case Study, Rambus
  • Transforming Simulators into Implementations, University of Texas – Austin
  • Using Algorithmic Test Generation in a Constrained Random Test Environment, Ericsson
  • Visualizing Debugging Using Transaction Explorer in SOC System Verification, Marvell Semiconductor

User Track – Back End

  • A Generic Clock Domain Crossing Verification Flow, Advanced Micro Devices
  • A Simple Design Rule Check for DP Decomposition, National Taiwan University
  • Algorithm for Analyzing Timing Hot-Spots, eInfochips
  • An On-Chip Variation Monitor Methodology Using Cell-Based P&R Flow, Faraday Technology
  • Application and Extraction of IC Package Electrical Models for Support of Multi-Domain Power and Signal Integrity Analysis, Freescale Semiconductor, Sigrity
  • Applications of Platform Explorer, Integrator and Verifier in SOC Designs, Samsung
  • Assertion Based Formal Verification in SOC Level, Wipro Technologies
  • Attacking Constraint Complexity in Verification IP Reuse, Cisco Systems, Synopsys
  • Automated Assertion Checking in Static Timing with IBM ASICs, IBM
  • Case Study of Diagnosing Compound Hold-Time Violations, Realtek Semiconductor, Mentor Graphics
  • Design Profiling – Modeling the ASIC Design Process, IBM
  • Enhanced SDC Support for Relative Timing Designs, University of Southern California, University of Utah
  • Hold Time ECO for Hierarchical Design, Global Unichip, Dorado Design Automation
  • Improving the Automation of the System in Package (SIP) Design Environment via a Standard and Open Data Format, IBM
  • Interconnect Explorer: A High-Level Power Estimation Tool for On-Chip Interconnects, Université de Bretagne
  • Managing Information Silos: Reducing Project Risk through Multi-Metric Tracking, Achilles Test Systems
  • Net-List Level Test Logic Insertion: Flow Automation for MBIST & Scan, Broadcom
  • Physical Implementation of Retention Cell Based Design, Atoptech
  • Sequential Clock Gating Optimization in GPU Designs with PowerPro CG, Advanced Micro Devices
  • Soft-Error-Rate Estimation in Sequential Circuits Utilizing a Scan ATPG Tool, Renesas Technology, Hitachi
  • Solving FPGA Clock-Domain Crossing Problems: A Real-World Success Story, North Pole Engineering, Honeywell International, Mentor Graphics
  • Static Timing Analysis of Single Track Circuits, University of Southern California, Sun Microsystems, Intel
  • Timing Closure in 65-Nanometer ASICs Using Statistical Static Timing Analysis Design Methodology, IBM
  • Using STA Information for Enhanced At-Speed ATPG, Freescale Semiconductor, Mentor Graphics

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors