CDC sequential reconvergence can be systematically verified without exhaustive manual review by using the circuit model in this methodology.
CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
A new clock-domain crossing methodology is described and results provided to show how automation delivers greater efficiency.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
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