Synopsys

March 1, 2016
Visual: cars speeding along a road

FMEA in automotive software development using virtual prototyping, physical modeling and simulation

How fault mode and effect analysis (FMEA) can be performed on a virtual prototype of an automotive system containing mechanical, electrical, analog and digital models, including the microcontroller running the same software as will be used in the car.
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March 1, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Exploiting the power of reset in formal verification

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
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February 22, 2016

Floorplanning complex SoCs with multiple levels of physical hierarchy

How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
January 27, 2016
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
January 20, 2016

Using end-to-end prototyping to reduce the impact of rising software content in SoCs

A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
January 19, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Reachable or reached, covered or coverable – is it just semantics?

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 12, 2016
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Processor configuration for low-power IoT applications

Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Expert Insight  |  Topics: IP - Assembly & Integration, Selection  |  Tags: , ,   |  Organizations:
January 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Thought you had verified your SoC? You probably only did half…

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
November 30, 2015

How to accelerate FPGA design productivity at every available step

How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design
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