The most expensive parts of today’s system-on-chip (SoC) design flow are where engineers must engage in direct manual effort or expend their energy making decisions. Unfortunately, far too much time and money are wasted on tasks that do not add value — such as trying to figure out if supposedly correct intellectual property (IP) is […]
Productivity levels for hardware design, specification, simulation and validation have been raised by the formal approval of IEEE 1800 SystemVerilog as an industry standard. Evolved from the Verilog hardware description language, SystemVerilog is now the language of choice for developing verification and design intellectual property (IP). As a result, EDA companies are progressing rapidly in […]
Designers thinking about low power and energy have a variety of strategies at their disposal. The most common are: Process/libraries (e.g. low-power processes/libraries; high and low threshold voltage cells; and voltage scaling); Power and voltage domains; Clock gating; Low-power optimized clock synthesis; Low-power synthesis (e.g. automatic insertion of operand isolation circuitry); Implementation optimizations (e.g. operand […]
Slowly but surely, the doors are opening. By that I mean that foundries and some IDMs are finally releasing significant amounts of fab process data for incorporation within the design for manufacturing content of EDA tools. Kudos must go to the IBM, Samsung and Chartered Semiconductor Manufacturing triumvirate for being first out of the gate. […]
As the third wave of the digital revolution finally gains momentum, the chip industry is breaking loose from its homogeneous telecom/PC-centric confines – where everyone’s product and box essentially looked and worked the same – into the arms of the fragmented consumer-centric heterogeneous multimedia, with significantly more brand names and lots of different price points. […]
Walden Rhines The official mission statement of the EDA Consortium (EDAC) says that the organization exists “to promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy.” EDAC’s chairman Wally Rhines, also chairman and CEO of Mentor Graphics, amplifies this by explaining that the […]
Kerry Bernstein When Kerry Bernstein, a 28-year IBM veteran, was first drafted to work on Big Blue’s development of 3D semiconductors, he admits he was a skeptic. “At first, I think I felt as though I’d got dragged into this program. I thought it wasn’t going anywhere. I thought it was going to go anywhere. […]
Joe Costello The dominant theme for DAC 2006 is multimedia, games and entertainment. So how does Cadence Design Systems founder and former CEO Joe Costello fit into that? He is after all giving the conference’s Monday keynote. Let’s do the ticklist. EDA credentials? Dated – he left Cadence in 1998 – but basically a ‘check’. […]
Design-for-manufacturability (DFM) has become pervasive and there is general agreement on the need to apply DFM at multiple stages of the design cycle. DFM techniques at the relatively mature 0.13um technology node entail well known enhancements such as contact and via redundancy, line-ends and borders, and wire spreading. Mature technology nodes achieve product yields which, […]
Ellen Sentovich As EDA Tech Forum went to press, the programme for 2006’s Design Automation Conference (July 24-28) in San Francisco was only just being made public. However, one thing was already clear. The event is set to be bigger than ever before. “We had been concerned about the move to July because of the […]
