Volume 3

September 1, 2006

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Putting together this latest edition of EDA Tech Forum was not unlike participating in chip design’s answer to Family Feud. A hundred design and semiconductor companies were asked what they considered the greatest challenge facing them today. And our survey said… ‘Verification’. Followed by ‘Mixed-Signal Verification’. Followed by ‘Debug’ with the caveat that they would […]

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September 1, 2006

SPIRIT achieves maturity with IP-XACT specifications

Introduction Complete system-on-chip (SoC) design assembly, configuration and verification environments emerged in the 1990s to address an increasing design gap between the capacity of silicon and the ability of engineering teams to fill that gap meaningfully with optimized system designs. Despite the need being addressed by these early environments, adoption was slow. In this context, […]

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September 1, 2006

Native SystemC Assertion mechanism with transaction and temporal assertion support

SystemC [1] is rapidly becoming the language of choice for ESL-centric design methodologies. It is set to become the framework for higher-level flows above today’s RTL, and has three key components: modeling, synthesis and verification. High-level modeling particularly demonstrates the language’s versatility and advantages. Strong progress is also being made in higher-level synthesis. However, our […]

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September 1, 2006

Last of the Pioneers

Wilf Corrigan ‘Epitaxy innovator’, ‘ASIC champion’, ‘SIA founder’. Those are a few of the descriptions you could apply to Wilf Corrigan. Another, until May, was ‘Last of the Pioneers’ – but then, after 46 years of involvement with major chip companies, Corrigan stepped down as chairman of LSI Logic, the company he set up with […]

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September 1, 2006

Embedded non-volatile configurable program storage

Processor program storage today Most of the microcontrollers currently on the market store program code in one of three ways: in ROM on the same chip as the MCU; in embedded flash memory on the same chip as the MCU; or as external flash memory whose contents are downloaded to the MCU. Each of these […]

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September 1, 2006

Coverage-driven verification for the analog domain

The verification of digital sub-systems is based on advanced techniques such as constraints capture, randomized or pseudo-randomized stimuli generation and results collection with functional coverage evaluation. The use of manually verified hand-coded analog block models within a digital verification environment has so far been sufficient. However, the move to greater levels of integration, shrinking process […]

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September 1, 2006

Advanced post-silicon verification and debug

More than 50% of highly complex systems-on-chip (SoCs) have functional issues at first silicon, issues that emerge after engineers have spent much time and money on verification and emulation. These issues delay time-to-ramp and cause significant losses of direct and indirect product revenue. All this demonstrates the need for efficient post-silicon debug methodologies and tools. […]

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September 1, 2006

A top-level verification methodology including power supply and signal check using mixed-signal simulation

The ‘state-of-the-art’ solution for wireless transceiver RF ICs is single chip CMOS, integrating digital, analog, and RF blocks on a single chip. The architectures involved require new and challenging approaches to verification. To understand these, we first need to look back at the history of the transceiver architectures used for wireless mobile phone implementations during […]

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September 1, 2006

Visibility enhancement for full-chip simulation

The most expensive parts of today’s system-on-chip (SoC) design flow are where engineers must engage in direct manual effort or expend their energy making decisions. Unfortunately, far too much time and money are wasted on tasks that do not add value — such as trying to figure out if supposedly correct intellectual property (IP) is […]

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September 1, 2006

Verifying complexity with an all-encompassing methodology

The increased size and complexity of designs continues to push design and verification methodologies to progressively higher levels of abstraction. These upward shifts in abstraction tend to occur about every decade or so, and we are currently experiencing one in the shift from RTL to transaction-level modeling (TLM). Abstractions must eventually be converted back effectively […]

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