Productivity levels for hardware design, specification, simulation and validation have been raised by the formal approval of IEEE 1800 SystemVerilog as an industry standard. Evolved from the Verilog hardware description language, SystemVerilog is now the language of choice for developing verification and design intellectual property (IP). As a result, EDA companies are progressing rapidly in […]
Designers thinking about low power and energy have a variety of strategies at their disposal. The most common are: Process/libraries (e.g. low-power processes/libraries; high and low threshold voltage cells; and voltage scaling); Power and voltage domains; Clock gating; Low-power optimized clock synthesis; Low-power synthesis (e.g. automatic insertion of operand isolation circuitry); Implementation optimizations (e.g. operand […]
Slowly but surely, the doors are opening. By that I mean that foundries and some IDMs are finally releasing significant amounts of fab process data for incorporation within the design for manufacturing content of EDA tools. Kudos must go to the IBM, Samsung and Chartered Semiconductor Manufacturing triumvirate for being first out of the gate. […]
As the third wave of the digital revolution finally gains momentum, the chip industry is breaking loose from its homogeneous telecom/PC-centric confines – where everyone’s product and box essentially looked and worked the same – into the arms of the fragmented consumer-centric heterogeneous multimedia, with significantly more brand names and lots of different price points. […]
Walden Rhines The official mission statement of the EDA Consortium (EDAC) says that the organization exists “to promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy.” EDAC’s chairman Wally Rhines, also chairman and CEO of Mentor Graphics, amplifies this by explaining that the […]
Kerry Bernstein When Kerry Bernstein, a 28-year IBM veteran, was first drafted to work on Big Blue’s development of 3D semiconductors, he admits he was a skeptic. “At first, I think I felt as though I’d got dragged into this program. I thought it wasn’t going anywhere. I thought it was going to go anywhere. […]
DATE 06 (March 6-10) is the ninth edition of the Design Automation and Test in Europe conference and the organizers have again received a record number of submissions, this year 834. This reflects the fact that today DATE is not merely a European conference but has become a well-known global event, receiving paper proposals and […]
Introduction The emergence of the SystemVerilog and PSL assertion languages promises to improve the effectiveness of existing verification flows. First, assertions give better local observability of the functionality they represent. Second, the assertions augment the textual specification to provide a more formal, executable representation of the functionality. Third, since the assertion languages have common semantics […]
T he explosion in consumer electronics, especially in the wireless/handheld devices marketplace, has placed a tremendous technical and business burden on engineers in the design of these products. Design teams carry the responsibility of catering to often conflicting and always challenging product specifications. The product needs to be optimized on multiple demand vectors with little […]
The advent of extreme fine line processes at 130nm or less presents many challenges. On the back end, optimizing a design to manage physical effects such as power, heat, and timing is more daunting than ever. At the front end, implementing a system-on-chip’s (SoC) behavior and features is becoming equally difficult. The early exploration of […]
