A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.
Embedded multicore systems require engineers to make choices around the hardware and software architectures, approaches to certification and more. This is a guide to the trade-offs involved and how to best leverage your options.
In conversation with author and SEMICON West/ES Design West keynoter Bob Pearson on the challenges facing tech on external and internal communication.
This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
Application-specific processors can provide high performance for specialised tasks at low energy cost.
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
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