The ultimate wish-list

By Bill Joyner |  No Comments  |  Posted: June 1, 2005
Topics/Categories: EDA - Verification  |  Tags:

If you want to get a clear idea of just what is taxing engineers at any given time, you can do a lot worse than following the trends that emerge before each annual Design Automation Conference (DAC). “And this year, it is pretty clear that there are three things on everyone’s mind: power, system-level design and, of course, verification, and design for manufacturability,” says Bill Joyner, director of Computer-Aided Design and Test at the Semiconductor Research Corporation and the 2005 DAC general chair. “In addition, there’s a great deal going on in the embedded space.”

Indeed, 17 of the 57 sessions at this year’s conference – running June 13 thru 17 at the Anaheim Convention Center – consider ESL design and verification or/and embedded systems. “Gary [Smith of Gartner Dataquest] has been saying that system level was coming for quite a few DACs,” Joyner continues. “Now it looks like it really is here, high up on the agenda.”

Given these overall challenges, the volume of research and innovation in EDA is also continuing at a consistent level. The last two DACs saw a major ramping-up in terms of submissions, something one can probably and fairly infer to be a reflection of the difficulties raised by sub-micron process geometries.

“This year, we also saw well over 700 papers submitted, and that’s a very healthy level,” says Joyner.

So what are some of the specific issues that have arisen in some of the key areas which the DAC program will address.


In 2000 and 2001, DAC sessions focused on closing the speed gap between ASICs and custom silicon. This year, speakers from IBM, Cadence Design Systems, Stanford and Berkeley will look at the same question in terms of power (Session 16,Weds, June 15th, 8:30-10:00am, Room 207ABC), a reflection of changing priorities, if ever there was one.

In all, five dedicated power technical sessions are scheduled, and three more will look at the intersection with embedded systems. Topics being reviewed include leakage, dynamic voltage scaling, tradeoffs and estimation.

Design for manufacturability

The nasty surprises over yield at 90nm have forced DFM to centerstage. In drafting the 2005 DAC program, the conference’s panels committee, special sessions process, and the regular papers process all independently targeted the topic. As a result, DFM will feature in seven sessions during DAC 2005, against just two last year.

Certainly, engineers need more guidance in this increasingly important area. DFM can be a nebulous beast, prone to becoming enmeshed in the kind of jargon that should be alien to the practicalities of a design flow. It is also one of those areas where every ‘expert’ seems capable of providing his or her own definition. At the same time, it does raise important concepts – addressed in the DAC technical papers – that do mark it as having a separate nature from typical design processes: statistical optimization and variability, to name just two.

A special session, DFM and Variability (Thurs, June 16th, 2:00- 4:00pm Room 207ABC) aims to provide a useful primer through short talks that look at various aspects of the conceptual paradigm, followed by a 30-minute Q&A session. Speakers will participate from Texas Instruments, Intel, Qualcomm, PDF Solutions and the University of Michigan, Ann Arbor.

System-level design and verification

ESL is not only here and now, but it has brought with it the problematic conundrum that some silicon is taking longer to verify than it does to actually design.

With that in mind, one panel will specifically look at whether a methodology-based path can circumvent this ‘hell’, with speakers from Sony, Synopsys, Sun Microsystems, STMicroelectronics and Jasper Design Automation (Session 31,Weds, June 15, 4:30- 6:30pm, Room 207ABC).

In all, 10 sessions will look at the topic from a variety of angles, several offering practical war-stories from the ESL front. Meanwhile, a second special session (Session 36, Thurs, June 16, 2005, 8:30-10:00am, Room 207ABC), will look at it in the context of developing practical flows for ASICs, DSPs and FPGA.

Wireless Design

This year, DAC is also launching it first Theme Day.Wednesday (June 15th) offers a series of events for designers working specifically on wireless chip design for wireless communication products and devices.

A centerpiece of the program will feature the best wireless papers from the ISSCC conference earlier this year (Weds, June 15, 2005, 4:30-6:30pm, Room 210AB) with contributions from companies such as ST, TI and Engim.


We preview Bernard Meyerson’s keynote address at this year’s DAC on pages 8-10. Some sparks are sure to fly there, and the conference’s other main speaker is also looking to challenge the audience.

Ron Rohrer, corporate vice president, Advanced Research and Development at Cadence Design Systems, has chosen the provocative topic, ‘Innovation in the EDA business need not be an oxymoron’ (Thurs, June 16, 2005, 12:45-1:45pm, Ballroom ABC).

He will describe a renewable model for EDA innovation based in part on a five step process: problem to prototype, to partnership, to product and, finally, to proliferation. The full program for DAC’s 42nd edition, including a personal planner, is available online at

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