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June 10, 2014

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

Article | Topics: PCB - Design Integrity, EDA - IC Implementation | Tags: advanced packaging, DAC 2014, finFET, high-density interconnect, power integrity, Serial IO, signal integrity | Organizations: Altera, Cadence Design Systems, Cisco, GlobalFoundries, Intel

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