OVM/UVM

October 11, 2013
Axel Scherer is a solutions architect at Cadence Design Systems in Massachusetts, leading the Incisive Product Expert Team for testbenches in general and the Universal Verification Methodology (UVM) in particular.

Learn the tricks of the UVM Register Layer

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
July 31, 2013
Featured image of ASIC chip plot - Dot Hill case study

RAID vendor Dot Hill adopts OVM flow for reliability

How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , ,   |  Organizations: ,
August 23, 2011

Bridging the analog-digital divide for verification

Bridging the analog-digital divide is tough, particularly when it comes to verification. The two domains are marked by a host of differences with regard to tools, methodologies and the basic means of developing and testing designs. Analog engineers do most of their work by building and moving graphics while their digital counterparts do most of [...]
Article  |  Topics: EDA - Verification  |  Tags: ,
August 23, 2011

The Universal Verification Methodology: ready, set, deploy

Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
Article  |  Topics: EDA - ESL  |  Tags: , ,   |  Organizations: , ,
February 25, 2011

Firmware verification using SystemVerilog OVM

Your current verification strategy, no matter how robust, may not always satisfy the latest demands placed upon it given the rate of change in semiconductor design. To stay at the forefront of innovation, you must be willing and able to take advantage of the potential in emerging and evolving technologies. It is not simply that […]

Article  |  Topics: EDA - Verification  |  Tags: , ,
February 25, 2011

Planning reset strategies: flow and functionality in OVM verification components

The article describes a methodology and appropriate code for developing a reset strategy that will work within a verification process. Specifically, the proposal has been drafted within the terms of the Open Verification Methodology.
Article  |  Topics: EDA - Verification  |  Tags: ,
February 25, 2011

OVM testbench API for accelerating coverage closure

Constrained random testbenches excel at quickly hitting the majority of coverage but their effectiveness trails off as coverage closure nears completion. This paper describes a testbench API that sits on top of OVM sequences allowing the existing constrained random infrastructure to be guided, enabling faster, more efficient coverage closure. Design and verification engineers can use [...]
Article  |  Topics: EDA - Verification  |  Tags: , , ,
September 2, 2009

Part 3 – A unified, scalable SystemVerilog approach to chip and subsystem verification

The article describes LSI’s work on the use of a single SystemVerilog-based (SV) verification environment for both the chip and its submodules. The environment is based on SV’s Advanced Verification Methodology (AVM) libraries, although alternatives are available. One particular reason for choosing AVM was that LSI wanted to leverage its transaction-level modeling capabilities as well […]

Article  |  Topics: EDA - Verification  |  Tags: , , ,
December 1, 2008

Tightening the loop on coverage closure

The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so […]

Article  |  Topics: EDA - Verification  |  Tags: , , ,
September 1, 2008

Building reusable verification environments with OVM

This article reviews the reuse potential within the Open Verification Methodology, with special focus on four particularly fruitful areas: testbench architecture, testbench configuration control, sequences, and class factories.

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