internet infrastructure


September 17, 2014

Web tool simplifies PCB-level clock-tree choices

Silicon Labs has developed a new type of parametric search tool that focuses on the selection of clock generators and jitter attenuators, making it easier to match them and downstream devices to the SoCs being designed into a PCB.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors