Putting together this latest edition of EDA Tech Forum was not unlike participating in chip design’s answer to Family Feud. A hundred design and semiconductor companies were asked what they considered the greatest challenge facing them today. And our survey said… ‘Verification’. Followed by ‘Mixed-Signal Verification’. Followed by ‘Debug’ with the caveat that they would like to work that into the verification and simulation process.
So, what happened to the other hot buttons such as, say, design for manufacturing? Well, it is still very much there but the thinking now may be that increasingly comprehensive tools are emerging — and foundries are cooperating with EDA vendors — so that the industry feels more confidence about addressing the problem.
IP re-use is another big issue in the system-on-chip era. But, again, cross-industry and multi-vendor collaborations are now delivering. Our article from The SPIRIT Consortium demonstrates clear progress — with hard data on improved productivity — and sets out a roadmap of viable future deliverables.
But, out of a record eight technical articles in this edition, five address verification directly — offering perspectives at various stages within the design flow — while two others consider the interplay between debug and verification. And this is by no means representative of the submissions we received — verification took up an even higher percentage.
The critical issue is time management. What techniques are there to either address this thorny problem early or attack it on a controlled basis so that it has the least impact on time-to-market? Say what you like about exponential complexity, it really is all about the Benjamins. In that respect, we hope that what you read over the next forty or so pages will spark ideas about improving your own design flow. The good news, as you will discover, is that there is a lot of original and innovative thinking out there.
Finally, a shameless plug. Summer is but a memory and as business cranks up again — does it ever really stop? — our latest EDA Tech Forum events in North America have opened for registration.
They feature hands-on workshops where you can try out the latest tools, and dedicated technical sessions on areas such as functional verification, DFM and ESL. We will be in Santa Clara on October 9 and in Boston on October 23.
I met many of you at the same events last year and hope to do those in 2006.