Volume 3
Power under control
In late 2001, Nick Baker and other members of the Ultimate TV team at Microsoft learned that the company was ending development work on the product. For a still youthful engineer whose curriculum vitae already took in some ill-fated early-days video card work at Apple and the short-lived 3DO games console, Baker could have been […]
Left shifting DFM analysis into the PCB design flow
What do we mean by a ‘left shift’ in design for manufacturing (DFM) analysis? Think of it as moving the DFM analysis from a tool run by the manufacturer into an integrated solution within the printed circuit board (PCB) design system. It is a major advance in the design of PCBs, allowing users to ultimately […]
Leakage power optimization for a wireless comms SoC
Leakage has become a critical concern for sub-100nm silicon process technologies. It had started to become a significant factor in a chip’s overall power profile at 130nm, but by 90nm things had worsened with leakage accounting for perhaps 30% of a chip’s total power consumption. At 65nm, leakage represents more than 50% of power consumption. […]
Design of SoG with p-SI TFTs using AMS simulation for AMOLEDs
The use of poly-Si TFTs for active matrix OLEDs (AMOLEDs) allows peripheral circuits to be integrated on a glass substrate at low cost and reduces the number of external driver ICs. The prospect of such integration means it is likely that emerging system-on-glass (SOG) design projects will feature both analog and digital blocks, such as […]
Common pitfalls in PCI Express design
PCI Express is a point-to-point communications interface. It is neither an evolved nor enhanced form of PCI or PCI-X, but, essentially, a high speed, low voltage, differential serial pathway for communication between two devices, although it uses the same programming model as its predecessors. It employs a protocol that allows devices to communicate simultaneously by […]
Using self-timed interconnect to accelerate SoC timing closure
Timing closure is one of the major problems faced by SoC designers. The inclusion of several, often diverse, IP cores that need to communicate with each other on a chip makes it difficult for a designer to meet the complex timing requirements between these cores. Furthermore, as process nodes shrink, process variability becomes a more […]
Start here
Simple question. But it’s one aimed specifically at the designers. In the last five years, have you ever been to the Consumer Electronics Show in Las Vegas – or, indeed, any of its international equivalents like CeBit in Hanover? The IDMs – Sony, Toshiba, IBM et al – will have hundreds of people at these […]
Silicon carrier for computer systems
Applications ranging from gaming to digital media to data analytics continue to grow more complex and constantly demand increasing computing power from computer systems. Historic growth in microprocessor performance has primarily been responsible for assuring a steady growth in the computing power of computer systems. Traditionally, this growing performance has been sustained by scaling down […]
Reducing power demands with specialized coprocessors
Consumer electronics is a difficult business.Market windows open and close quickly. Cost is critical. Requirements change unpredictably. Risk is high. Functionality and performance increase with every product generation, while both manufacturing-limitations and feature-driven demand require low power implementations. Of all these, power constraints have the largest impact on current product architectures. As CMOS reaches its […]
PLATINUM SPONSORS
View All Sponsors