The paper discusses the simulation, design, and test of software-defined radios (SDRs), initially using a legacy 16QAM waveform, followed by a new SDR waveform -orthogonal frequency division multiple access (OFDMA). The SDR system’s error vector magnitude (EVM) is first analyzed and its performance is compared with the legacy waveform results. The implementation also includes the […]
Every economic wobble sees technology’s ciabattering classes put down their salad-stuffed sandwiches and decaf mochas to forewarn of threats to venture capital (VC) investment. And so has it gone since the sub-prime mortgage bug finally bit. OK, as a public service, here’s the skinny. We surveyed 20 VC firms and corporate venturing arms and got […]
Today more than ever, the difference between design success and failure resides in engineers’ ability to master all critical design factors at once. Meanwhile, systems-on-chip (SoCs) represent a multidisciplinary challenge that spans the entire flow from architecture through design to test and finally mass production. For portable applications in particular, SoCs present especially stringent constraints […]
Since the early 1980s,most of the semiconductor business has been enthralled by the microprocessor, the PC and commodity DRAMs. For all the talk of potential ‘better markets’ and ‘more profitable businesses to be in’, PCs and their brethren came to represent 35- 40% of the industry’s output. They constituted the prime platform for not only […]
While DDR3 SDRAM offers speed and low-power benefits, the fly-by termination topology defined by the JEDEC specification for DDR3 SDRAM DIMMs creates interesting challenges for FPGAs. The JEDEC topology significantly reduces the simultaneous switching noise that plagues high-frequency parallel interfaces, but also introduces the need for read and write leveling to compensate for the deliberate […]
For simulation to correctly predict silicon behavior, the logic implementing a design should adhere to the setup and hold constraints specified for clocked elements. However, with multiple asynchronous clocks on a single chip driving logic, designers cannot help but violate setup and hold constraints. This causes metastability, which in its turn leads to non-deterministic delays […]
The article describes and illustrates, by way of a case study, an innovative approach to functional verification. It enables the reuse of test patterns through the coordinated combination of a top-level testbench and subordinate testbench modules. It is based on a new add-on tool, VTrac+, that extends Mentor Graphics’ ModelSim/Questa software to stimulate, compare and […]
The paper outlines the criteria upon which an OEM should make its selection of a third-party PCB design supplier. It groups these into three main categories. Staff with appropriate technical and communications skills. Comprehensive and fully documented design processes (ranging from the use of consistent design strategies to approaches to component library maintenance). Tool support […]
Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]