Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
low-power design
DVFS and body bias
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Near-threshold and subthreshold logic
By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
Virtualization
Virtualization makes it possible to run multiple operating system images on one processor core – with benefits for memory protection, power efficiency and cost reduction.