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14nm/16nm
14nm/16nm
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(16)
Articles
(14)
Guides
(2)
May 28, 2015
Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Guide | Topics:
EDA - IC Implementation
| Tags:
10nm
,
14nm/16nm
,
dynamic logic
,
finFET
,
glitch
,
low-power design
,
multibit merging
,
placement
,
synthesis
May 19, 2014
14nm/16nm processes
The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.
Guide | Topics:
EDA - IC Implementation
| Tags:
14nm/16nm
,
cell pin access
,
double patterning
,
interconnect resistance
,
layout dependent effect (LDE)
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