ARM to re-spin Cortex for AI and servers

By Chris Edwards |  No Comments  |  Posted: March 21, 2017
Topics/Categories: Blog - IP  |  Tags: , , , , ,  | Organizations:

ARM has pulled together a number of forthcoming changes to its Cortex processor and Big-Little cluster architectures under the umbrella title DynamIQ, claiming they will support the increasing use of artificial intelligence (AI) algorithms in servers and embedded control.

Although the company plans to add dedicated instructions to handle AI algorithms that appear to be focused on improving accesses to memory – the biggest contributor to latency and energy consumption in neural network-type code – the enhancements touted for DynamIQ over the existing v8 architecture focus on energy and cluster management.

ARM envisages much a greater variety of cores being brought together into Big-Little clusters, with each processor being activated and put to sleep at frequent intervals. The company says it has developed ways to reduce the time it takes to wake up a core, transfer data to it and then deactivate it once its short-term task has completed.

Memory will come under the same kind of energy-management regime, claims ARM product manager Govind Wathan: “Autonomous CPU memory power management, a way to intelligently adapt to the amount of local memory available to the CPUs depending on the type of application running, is another key feature in the technology. Applications that demand a high amount of compute performance, such as augmented reality, will have the maximum amount of local memory at its dispense, while lighter applications, such as music streaming, will have a scaled-back amount of local memory, saving CPU memory power.”

The processors developed as part of the DynamIQ family will have a new port to support custom accelerators. An redesigned accelerator interface, though optimised for low energy rather than the high performance expected from server and AI applications, is being added to the low-end Cortex-M family.

The company claims over the next three to five years, the changes will provide a 50-fold improvement in AI code performance, but it is unclear as to how the speed boost will be assigned to new instructions, the availability of additional cores and accelerators.

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