Consider your options for future nodes

By Steffen Schulze |  No Comments  |  Posted: January 13, 2014
Topics/Categories: EDA - DFM  |  Tags: , , , , , , ,  | Organizations:

Steffen Schulze is director of marketing for Calibre Mask Data Preparation at Mentor GraphicsSteffen Schulze is currently with the Design to Silicon Division of Mentor Graphics. He is the director of marketing for Calibre Mask Data Preparation and platform applications serving customers in mask and IC manufacturing.

As a lithography technology that can take silicon into the sub-10nm era, extreme ultraviolet (EUV) is the strongest candidate. But we have to achieve high throughput and high quality results with EUV before the industry can commit to use it. In the meantime, we have to work out how to maintain the pace of Moore’s Law and move from 20nm to 14nm and beyond. The time has come to think about the other options.

EUV has missed several entrance points for adoption in production fabrication. EUV is unlikely to be used for 14nm production and may not be fully ready for the beginning of the 10nm node, although for 8nm EUV is a strong contender. What do we do to bridge that gap? And also to be ready in case EUV become available sooner than currently expected? We have to plan for the various possibilities.

There are other options the industry can use and now is the time to think about how we can incorporate those into the design-for-manufacture (DFM) flow. We have already started production using double patterning.

Multiple patterning

To push the capabilities of 193nm further, the industry is now examining the possibility of using triple and even quadruple patterning, with potential for repeated litho-etch sequences, similar to the LELE double-patterning techniques in use for logic, and self-aligned multiple pattering (SAMP). Even electron-beam patterning may be incorporated into manufacturing if throughput issues can be overcome. Each technology has its own challenges and advantages – attributes that may lead to them being used for different layers on an individual SoC product.

The key question is how these advanced patterning techniques fit with design. LELE-style pitch-splitting techniques have a more direct correlation with the original design data than those made using SAMP or even more advanced forms of chemically assisted self-aligned patterning such as directed self-assembly (DSA). With these techniques, the patterning is more disconnected from the design than ever. This will put pressure on the DFM flow as fixing errors to deal with potential yield issues becomes more difficult. Tools will be required to allow the mapping of patterning errors back to the design so that the designer can apply intelligent fixes without having to understand the minutiae of increasingly complex design rules.

Tools such as those from Mentor already understand the core requirements for double and multiple patterning. Technology built into the DFM flow for LELE double pattering, for example, already analyzes optical proximity correction (OPC) not just for individual layers but across the complementary patterning layers to ensure that corrections made for one mask do not adversely affect the other. Changes can be applied to one mask that will be reflected on the others.

Mask corrections

Techniques in use today such as inverse lithography will be propagated down to these new nodes to allow corrections to be injected at a yield hotspot without forcing a redesign at the layout and routing stages or process changes. Later changes to the process may allow aggressive techniques such as these to be relaxed and the design modified to take advantage of that. But the opportunity to fine-tune yields in complex multiple-patterned processes will provide design teams with a strong advantage.

The use of more patterning masks also introduces problems of critical dimension (CD) process control. The tolerances that need to be realised are becoming increasingly stringent. The effects seen in the process need to be modelled more precisely because errors that did not need to be considered in older processes now have to be taken into account.

A further consideration is the use of dummy fill. This has to get smarter. Whereas previously, fill could be applied in an unstructured way using primarily process-related constraints, the impact of fill on active circuits needs to be considered because of local and semi-local effects on device variability. Fill will need to be OPCed correctly and placed selectively based on models of what effect each type will have on the local environment.

In contrast to earlier process nodes where the industry had a clear idea of the future direction of lithography, the next couple of nodes are clouded with uncertainty. This is why companies such as Mentor are investing heavily in research on the impact that the different options have on DFM so that the ecosystem has access to effective solutions – whatever the players settle on.

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