Intel will reveal more details of its ‘Tri-Gate’ FinFET-based 22nm process at this year’s VLSI Symposium, which will, for the first time, overlap the Technology and Circuits symposia to reflect the increasing interdependence of the two aspects of IC design.
Intel says its 22nm process is in volume production. It uses a 3D transistor architecture that gives the gate greater electrostatic control of the transistor’s channel by surrounding it on three sides. Intel’s take on this approach, more widely known as FinFETs (Guide), uses a fully depleted channel, a third-generation HKMG stack technology, and strained-silicon techniques to achieve what is said to be the highest drive currents yet reported for NMOS and PMOS devices in volume manufacturing for given off-currents and voltage.
The company has proved the process by building a 380Mbit SRAM macro using three different cell designs, the fastest of which operates at 4.6GHz from a 1V supply. Intel also used the process to demonstrate its work on trading off between device and design limitations, in a paper that describes a digital adaptive clock distribution scheme for microprocessors. The circuit uses clock gating to counter the effect of drooping power rails on performance and energy efficiency. Intel says that its measurements on the procesor that uses the clocking scheme show up to a 31% improvement in throughput at voltages down to 0.6V.
An evening session will look at the evolution of the FinFET and other advanced transistor designs, such as ultra-thin body and ultra-thin BOX SOI, Ge and III-V transistors, tunnel FETs and other concepts.
Planar processes are not dead yet, though. A paper from the IBM-led International Semiconductor Development Alliance (ISDA) will describe a 20nm planar bulk CMOS technology for low-power mobile applications which, it is claimed, achieves nearly twice the density and drive currents of 28nm offerings. The process also offers multiple threshold voltages, high-speed input/output devices, and high-density/high-speed static memory. Papers from the ISDA and equipment vendor Allied Materials will also seek to demonstrate that the ‘gate-last’ process used in this process will continue to scale down, even to 11nm gates.
The ISDA has also been working on high performance SOI CMOS at 22nm, using an extremely thin SOI layer (to reduce leakage and sensitivity to gate-length variations), which is strained to achieve the necessary performance by using in-situ-doped raised-source/drain and strained-channel processes.
There’s also a nod to an alternative future development path for low-voltage devices, in a paper from University of Tokyo researchers, who will report on the first sub-60nm III-V n-channel MOSFETs built on a silicon substrate. The devices, which are made from InGaAs and InAs-on-insulator on silcion substrates, are said to offer excellent control of short-channel effects and suppression of off-state leakage current. The carrier mobility enhancement and lower parasitic resistance made possible by moving to III-V materials has enabled higher transistor on-state currents.
The 2012 Symposium on VLSI Technology in Honolulu will run from 12 to 14 June, overlapping with the 2012 Symposium on VLSI Circuits, which runs from 13 to 15 June, and features some joint sessions. There will also be a silicon nanoelectronics workshop on 10 and 11 June.
In an interesting reflection of current uncertainty about the technical and business future of silicon electronics, Mike Mayberry of Intel will use his plenary address to discuss the future of CMOS technology scaling, and identify directions for novel switching devices and new methods for computation. In an evening session later in the week, the topic will whether VLSI innovation is dead, with experts from IBM, Intel, AMD, NTT, and MIT, Shizuoka and Stanford Universities discussing why companies in fields such as web software and servers/OEMs are in the headlines, while semiconductor companies are not. As the publicity material puts it “The question for discussion is, is VLSI semiconductor innovation fine, dead, dying, or does it just need a kick-start?”
Back at the sharp end, joint sessions will cover advanced device and circuit design co-optimization, for memory, 3D system integration, emerging non-volatile memory, advanced SRAM, design in scaled technologies and design enablement in scaled CMOS, and embedded memory.
Short courses will focus on 14nm CMOS technology and design co-optimization and memory; designing in advanced CMOS technologies; and ultra-low power SoC design for future mobile systems.
There will also be focus sessions on low-power and steep subthreshold technology, and flash memory.
Find out more here.