June 1, 2006
Ellen Sentovich As EDA Tech Forum went to press, the programme for 2006’s Design Automation Conference (July 24-28) in San Francisco was only just being made public. However, one thing was already clear. The event is set to be bigger than ever before. “We had been concerned about the move to July because of the […]
June 1, 2006
Analyses made by semiconductor manufacturers have demonstrated that maintaining pattern fidelity is critical, and that this task faces increasing limitations at the 65nm process node and below. At these technology nodes, even the most advanced resolution enhancement technologies (RET) have a difficult time with certain layout topologies. When the impact of this is observed across […]
Article | Tags:
June 1, 2006
Why are more chips late to market and cost three times more to design at 90-nanometer (nm) than at 130nm? Today’s ASSPs and ASICs are huge, approaching one billion transistors, with clock speeds exceeding 1-GHz. Engineers struggle to manage the complexity of devices that achieve these levels of performance and size. A natural reaction to […]
Article | Tags:
June 1, 2006
Engineers on the leading edge of nanometer design are dealing with physical effects that change the way mixed-signal ICs are verified – in timing, power, reliability and yield. With the IC verification effort accounting for 60-80% of the development cycle, choosing and deploying the right mixed-signal verification solution can significantly improve productivity and the return […]
Article | Tags:
June 1, 2006
When migrating from FPGA prototype to ASIC, engineers need to interface with multiple silicon and software vendors. Designing with FPGAs often requires the use of several software platforms, including front-end synthesis tools, FPGA software development tools, and verification and timing analysis tools. Migrating to an ASIC platform involves using a parallel design flow with different […]
Article | Tags:
June 1, 2006
Productivity levels for hardware design, specification, simulation and validation have been raised by the formal approval of IEEE 1800 SystemVerilog as an industry standard. Evolved from the Verilog hardware description language, SystemVerilog is now the language of choice for developing verification and design intellectual property (IP). As a result, EDA companies are progressing rapidly in […]
Article | Tags:
June 1, 2006
Designers thinking about low power and energy have a variety of strategies at their disposal. The most common are: Process/libraries (e.g. low-power processes/libraries; high and low threshold voltage cells; and voltage scaling); Power and voltage domains; Clock gating; Low-power optimized clock synthesis; Low-power synthesis (e.g. automatic insertion of operand isolation circuitry); Implementation optimizations (e.g. operand […]
Article | Tags:
June 1, 2006
Slowly but surely, the doors are opening. By that I mean that foundries and some IDMs are finally releasing significant amounts of fab process data for incorporation within the design for manufacturing content of EDA tools. Kudos must go to the IBM, Samsung and Chartered Semiconductor Manufacturing triumvirate for being first out of the gate. […]
Article | Tags:
June 1, 2006
As the third wave of the digital revolution finally gains momentum, the chip industry is breaking loose from its homogeneous telecom/PC-centric confines – where everyone’s product and box essentially looked and worked the same – into the arms of the fragmented consumer-centric heterogeneous multimedia, with significantly more brand names and lots of different price points. […]
June 1, 2006
Walden Rhines The official mission statement of the EDA Consortium (EDAC) says that the organization exists “to promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy.” EDAC’s chairman Wally Rhines, also chairman and CEO of Mentor Graphics, amplifies this by explaining that the […]