Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
Architecture & Design
Optimizing power and performance trade-offs in CNN implementations for embedded vision
High-performance vision-processing algorithms need optimized CNN engines to deliver the right performance within the power budget of embedded applications.
Bringing AI into our lives
Using specialised processors to implement key AI computation tasks such as CNNs.
Using hardware secure modules to protect SoCs
Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust
Choosing between DDR4 and HBM in memory-intensive applications
Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
Fighting the war of escalation in embedded systems security
The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.
Supporting higher-resolution displays without major system redesign
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
Using CCIX to implement cache coherent heterogeneous multiprocessor systems
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Applying sub-threshold circuit techniques to IoT device design
Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
High-resolution visual recognition needs high-performance CNNs
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.