How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Introducing one of the latest refinements of formal and showing how ArterisIP and Oski Technology used the strategy on an ARM-based design.
Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
- Article How HLS is giving shape to glasses-free 3DTV
- Expert Insight The Wally Rhines interview – Part One: Mentor as a Siemens business
- Expert Insight DVCon China launches this April in Shanghai
- Article Improve custom/AMS design and productivity with in-design DRC
- Expert Insight Assessing the true cost of node transitions
- Expert Insight Making security a profit center for silicon
View All Sponsors