Time to take up the 3D integration challenge

By Marco Casale-Rossi |  No Comments  |  Posted: April 10, 2013
Topics/Categories: EDA - DFM, IC Implementation  |  Tags: , , ,  | Organizations:

Marco Casale-Rossi, senior product marketing manager for 3DIC, SynopsysMarco Casale-Rossi is senior product marketing manager for 3DIC at Synopsys. He joined Synopsys in 2005, after 20 years at STMicroelectronics’ Central R&D. During the past few years, as product marketing manager for the Galaxy Implementation Platform, Marco has contributed in building Synopsys’ vision of the nanometer design and technology roadmap.

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing. What’s missing is designers who are willing to take the first step, perhaps by using a 2.5D-IC integration technology, such as a silicon interposer, to begin with. Those who do so will be among the first to benefit from this new form of integration, as well as having the opportunity to help shape the emerging 3DIC ecosystem to their needs.

3DIC integration solves a number of emerging design issues, including the rising cost of leading-edge processes, the limited availability of such processes for any but the largest-volume designs, and the increasing imbalance between the number of I/O pins, and the amount of logic that can be implemented on a chip. 3DIC technologies also bring opportunities for new forms of integration, such as heterogeneous systems that tightly couple die produced on different processes, or which bring together, besides logic, MEMS, and optical circuits in ‘More than Moore’ configurations.

Such integration efforts can open up new markets – when Sony used a 3DIC integration technology to improve the performance of its camera chips, the new sensors found new applications. 3DIC integration can also enable users to build devices at densities that would otherwise only be achievable with future process generations – as Xilinx has for its largest FPGAs, by mounting multiple FPGA die on a silicon interposer. And they can mitigate wider systemic issues, for example enabling designers to use smaller PCBs with fewer layers by shifting a lot of the functional integration into the third dimension.

Slow uptake

The uptake of 3DIC integration technologies lags the forecasts that analysts made for it in 2007 by three years. Why the delay? Apart from a global financial crisis that increased everyone’s aversion to risk, industry watchers point to a number of issues. Homogeneous 2.5DIC integration, where one company controls all the die that are to be integrated, works, as Xilinx has proved. But heterogeneous integration, using die from many sources, throws up issues such modeling, testability, procurement and liability.

3DIC integration, in which active die are stacked on top of each other and interconnected using through silicon via (TSVs), poses additional challenges. The TSVs are relatively big compared to the logic that they are connecting, so 1,000 of them, including the surrounding keep-out zone, take the same silicon real estate of 1,000,000 ASIC gates at 32/28nm, and may not make sense, at least for some applications. The aspect ratio of TSVs is also limited, which means that active wafers have to be drastically thinned, thus creating a handling problem in manufacture. And stacking die may cause thermal issues, as yet unresolved.

The short-term alternative is to work with 2.5DIC integration techniques, using a silicon interposer as what is effectively a miniature PCB with rich routing resources to interconnect the die, and TSVs to connect the resultant circuit to a package.

We know this works – it’s how Xilinx is building its biggest FPGAs – and we’re evolving the tool chain to develop such designs rapidly by extending the tools we offer for IC design to handle the special needs of 3DIC design. We can’t automate away all the intricacies of this new integration technology – applying it remains a multidisciplinary challenge – but the claim made three years ago, that there are no tools, no longer stands.

Removing obstacles to adoption

So what is holding back the uptake of 3DIC integration technologies, and especially the 2.5DIC techniques that offer advantages in their own right as well as acting as a pathfinder to true 3DIC integration? Part of the problem is the supply chain, which is still developing. Part of it is the need for new players to emerge to take their place in the evolving 3DIC ecosystem. And part of it is the need for new business models, which match the technical advantages of the approach to a commercial opportunity.

One way forward for 3DIC integration is for more people to join the ranks of designers, foundries, die manufacturers, tools vendors and others who are working together to overcome the remaining issues. They’ll be among the first to master the technology and take advantage of the market opportunities it brings.

If you’re facing a difficult integration issue, have a design that is increasingly I/O bound, or want to explore new ways to build systems, consider 3DIC integration as one way forward. When you’ve done your analysis, and if the technology seems right for you, have the courage of your convictions and commit to its use. In innovation, especially, fortune favors the brave.

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