IMEC says it has begun work on a 14nm test chip based on a process design kit (PDK) that the Belgian research institute has developed as part of its work on future processes – and one that includes finFETs.
The PDK reflects a number of choices that chipmakers will face when they get to this node and not just whether they use finFETs or planar transistors but the materials that will be in the transistor channel and how those features will make it onto the wafer. Although it is not in the initial release of the 14nm PDK, IMEC says later versions will include support for high-mobility channel materials. The research institute has not indicated which ones but III-V compound semiconductors or germanium are possible as alternatives to good old silicon.
Another choice will be the one of lithography. Although Peter Jenkins, vice president of marketing at ASML claimed at the recent ISS Europe conference in Munich, Germany that EUV would be ready for production volumes in two years, fab owners are still hedging their bets with plans that encompass immersion lithography with multiple patterning with a possible switch to EUV if it turns out to be ready on time and offer lower cost production.
The choice of lithography is likely to have a direct effect on the transistor shapes and quality – it will be tough to reduce line-edge roughness with optical lithography and EUV has some interesting knock-on effects of its own. So, the IMEC PDK has been designed to reflect the likely differences in transistor behaviour that will be seen using these different manufacturing methods.
The test chip, which is planned to go into production in the second half of 2012, will be used to test assumptions about device, interconnect and process behaviour using structures that meet the area budgets expected of the 14nm node.
The PDK is the result of work in IMEC’s Insite program, which provides its partners with early access to process R&D work.