The physical design challenges of 20nm processes

By Tong Gao |  2 Comments  |  Posted: October 11, 2012
Topics/Categories: EDA - DFM  |  Tags: , , , ,  | Organizations:

Tong GaoDr Tong Gao is a Synopsys Fellow. Tong has been with Synopsys for more than eight years leading routing technologies and is the architect of IC Compiler Zroute. Before Synopsys, Tong was responsible for routing technologies in Monterey Design Systems, Avant!, and Silicon Graphics.

The 20nm process node is making it more difficult to tackle the existing challenges of IC design, as well as introducing significant challenges of its own.

The biggest challenge at 20nm is manufacturability. Before we reached 20nm, ensuring what was designed could also be made was mainly achieved using design rules. The number of rules for 20nm processes is more than twice the number required at 28nm, and the 20nm rules are more complex in scope and influence. But applying design rules at the end of the process won’t be enough to ensure that chips can be made: designers will have to take manufacturability issues into account much earlier in the process.

Why is this? What went wrong?

To keep up with Moore’s Law, the minimum metal pitch of a 20nm process is just 64nm – too small to be resolved using current 193nm optical lithography systems. The solution is to split the densest features of a chip onto two distinct masks, which are then etched and formed separately. The resultant, interleaved patterns form the densest features of the process. Meeting these double-patterning requirements has a profound effect on the entire place-and-route flow. The key to overcoming these challenges is to intelligently manage the interactions of these shrinking shapes.

Splitting these shapes onto two masks can be done in many ways, and each approach has challenges, limitations and benefits. The most tractable approach for an EDA implementation is the ‘two colorable solution’, in which the challenge of decomposing the design in real time can be avoided, if we instead focus on not creating any ‘odd-cycles’ in the proposed metalization. These ‘odd-cycles’ make it impossible to decompose (split) a layout into the aforementioned two mask sets or ‘colors’. You can understand this if you imagine having an odd number of metal shapes facing each other - it is impossible to give each shape one of two colors without giving two adjacent shapes the same color. This forms the ‘cycle’ part and as we are trying to decompose to ‘two’ colors, it takes an odd number at the requisite highest density to create an ‘odd-cycle’.

Library designers have long known about routability challenges but at 20nm even more constraints must be met if the busy pin-access layers are to be decomposed. The real battle is to balance the desire to create the smallest, most closely packed cells with their associated smallest pins and the need for easy-to-access cells that will make it easy to decompose a layout. With aggressive cell design it is easy to create odd cycles when lots of shapes exist close together and the patterns are irregular. This is exactly what standard-cell pin layers generally look like. Keeping the pins aligned and running in the preferred routing direction allows the router more flexibility to fix any odd cycles. This helps maximize routing density.

From the above you can see that by far the biggest design challenge at 20nm is that of routing. To take advantage of the density gains of moving to 20nm, you want to route as many wires as possible at the 64nm minimum pitch. Splitting such dense wiring onto two masks works well for regular, straight wiring but if there is a discontinuity in the routing pattern – an off-grid complex pin access, wrong-way routing through a dense channel, proximity to wide via overhangs or line ends – it may be impossible to do the decomposition. Also, unlike most design rules that are bounded by local area, odd-cycles are effectively unbounded and can reach across an entire chip. Dealing effectively with this unbounded problem in an otherwise bounded routing process is crucial to ensuring that the router can offer the productivity necessary to enable gigascale designs.

The obvious fix to decomposition issues is to space out the wiring, but this negates the density advantage of moving to 20nm. The answer is to intelligently space and re-route the wiring to achieve the best usage of routing resources that can still be decomposed onto two masks. This takes active and effective management of both total and local congestion - especially in narrow channels and around difficult pin access - to ensure the best chance of meeting design rules and ensuring manufacturability. The key is to make the routing patterns as simple as possible throughout, which usually also enhances device yield.

The shift to 20nm processes is making accommodating the physics of the manufacturing process an increasingly important facet of design. With these challenges comes the excitement that my team and I have enjoyed developing IC Compiler into what we feel is the industry’s leading solution to the double-patterning challenges described above. After all, it’s up to us EDA tool vendors to make the job of chip design as easy as possible so that designers can focus on making the most of the potential of the new process nodes.

Author

Dr Tong Gao is a Synopsys Fellow. Tong has been with Synopsys for more than eight years leading routing technologies and is the architect of IC Compiler Zroute. Before coming to Synopsys, Tong was responsible for routing technologies at Monterey Design Systems, Avant!, and Silicon Graphics. He received his BS, MS, and Ph.D. degrees in Computer Science from University of Illinois at Urbana-Champaign

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2 Responses to The physical design challenges of 20nm processes

  1. raviteja on October 14, 2012

    20nM process design challenges

  2. Pingback: EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes | Tech Design Forums

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