Tanner embraces OpenAccess

By Chris Edwards |  No Comments  |  Posted: March 7, 2013
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

Tanner EDA has completed the port of its HiPer Silicon design suite to work with the OpenAccess IC-design database, culminating in the release of version 16.

“There are two really strong industry-wide motivators driving OpenAccess for Tanner and indeed for the industry,” said Paul Double, managing director of EDA Solutions, which represents Tanner in Europe. “The first of those is that it provides a means by which people can use a plethora of different tools without having to move information in and out of proprietary databases.

The second motivator, said Double, is foundry PDK support from foundries which is now largely through OpenAccess with either Cadence PCell support or the iPDK PyCell format.

Double claimed the work to port HiPer Silicon involved an extensive period of testing against real-world database with the help of some of the foundries to help guarantee interoperability.

“We’ve worked with several foundry partners to make sure we can work with the leading tools vendors seamlessly even though what they do is proprietary and not documented in the OpenAccess specification,” said Double.

The foundries and the Tanner groups went through an incremental process of passing design files between each other to test how the tools react to different PDKs and designs and adjusting the tools’ responses as errors were found. “Because we’ve had to take this approach we have been quite useful to the OpenAccess consortium because we have helped clean up the specs. And we wind up with perhaps a more robust implementation of OpenAccess than anyone else.

“The suite has been totally rearchitected to work with OpenAccess as the native database,” Double said. “But we don’t want to prohibit users from working with the Tanner database. We will continue to support the Tanner database.”

The reworking to OpenAccess has made it easier to support multiple users working on the same design, Double said, because the architecture of the environment now splits an individual project and its process data into multiple files.

“The other thing we have done is add a digital flow to the front end,” said Double. “We have partnered with companies who offer a similar approach to the market, such as offering perpetual licences.”

The two partners are Aldec, which offers both Verilog and VHDL simulation, and Incentia Design Systems for digital synthesis. The aim is to support users who are putting increasing amounts of digital logic into their analog- or RF-heavy designs. Digital assist logic is now a common feature of low-voltage, nanometre processes.

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