When looking at new architectures for low-power operation, it is easy to get fixated on one part of the design and ignore the ramifications for the rest of the system. The consequences of that are demonstrated in a paper that was presented at last year’s International Symposium on Low-Power Electronic Design in Japan that shows that the demands of subthreshold circuitry can have knock-on effects.
Rami Abdallah, Pradeep Shenoy, Naresh Shanbhag and Philip Krein from the University of Illinois at Urbana-Champaign looked at how dynamic voltage scaling affects not just processors and logic but the DC/DC converter used to supply power to the circuitry, and found that the minimum energy point is not where you expect to find it.
For logic circuits, there is a clear tradeoff between supply voltage, frequency and energy. Go too low in voltage and the static consumption takes over because the circuit is so slow it has to run for a long time. Go higher and the active power consumption of a faster circuit dominates. In between is the minimum energy point. Generally, for low-energy systems, the minimum operating point for logic lies just inside the subthreshold region.
However, the authors point to a 2010 paper in the Proceedings of the International Conference on Computer-Aided Design by Yu Pu and colleagues from the University of Tokyo which pointed out the way that DC/DC converter losses increase in the subthreshold region – potentially negating some of the power savings. As many system designers have found over the years, DC/DC converters work best when they have a reasonable amount of energy passing through them – they lose a large proportion of the energy when the electricity is just dribbling through.
The analysis by Abdallah and coworkers found that the DC/DC losses can be considerable, especially for heavily pipelined systems, which have been proposed as a way to overcome the throughput disadvantage of subthreshold operation. The result is to force the minimum energy point to somewhat higher voltages. However, increased parallelisation to improve cycle times can force the operating points for system and logic core closer to each other – it increases the total flow of energy through the system while it is operating.
The authors looked at reconfigurable architectures to help improve efficiency and found that these can result in better overall system power consumption compared with fixed logic – improving throughput in the subthreshold by a factor of eight.
It’s a while to wait for the ISPLED but there is still time to get a paper in. Paper submission for this year’s ISPLED closes at the end of this month.