3D IC is already making waves at DAC. At the Gary Smith EDA pre-DAC briefing, Mary Olsson took a conservative view, saying that the technology could be delayed for 5 years, even though many believe it will begin to appear in 2012.
She argued that the main challenge the technology faces is the fact that potential users already have other safe and workable options. Also, for example, through silicon via technology remains at the research rather than commercial implementation stage.
However, Atrenta and Belgian research agency Imec are taking a more optimistic view and are showing off an “advanced planning and partitioning design flow for heterogeneous 3D stacked ICs” at the conference (Booth #1643).
“The number of potential solutions for any given system design problem (e.g., front-to-front, front-to-back, silicon interposers, technology choice for slices, via configurations, partitioning, etc.) is very large,” their joint statement says.
“Exploring this solution space through multiple fill designs is simply too expensive and time-consumin. This makes it critically important to perform robust, accurate partitioning and prototyping early in the design process, well before detailed implementation begins.”
I’m lucky enough to have Atrenta’s Mike Gianfagna on our panel, “Who is Driving 3D IC and Why?”, when we’ll be sure to quiz him on the work with Imec. Mike’s joined by Sanjeev Sathe from GLOBAL FOUNDRIES, Rob Aitken from ARM, Simon Burke from Xilinx and Juan Rey from Mentor Graphics.
Join us, if you’re at DAC, at the Mentor booth #1542 at 11am tomorrow (Tuesday). If you can’t make it, we hope to post video of the panel soon after DAC.