This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.
Why are more companies turning to FPGA-based prototyping to assist them in bringing designs to fruition? The technique is not cheap, in terms of raw development and bring-up, nor is it without considerable challenges.
Beyond our old friends design complexity and time-to-market, we have identified three trends that are driving the segment: some established, some emerging and evolving. We can reduce them down to their role in lifting your ROI, an increasing number of standalone use-cases and physical prototyping’s greater integration within the design flow.
Commercial FPGA-based prototyping systems deliver better ROI
The market growth in commercial FPGA-based prototyping systems is largely due to a decline in the use of custom/in-house boards. Engineering managers now recognize that any proper accounting of the cost of home-grown systems is not just a matter of adding up the component BoM and PCB fabrication costs. You must also include the opportunity cost of engineers being applied to this task instead of working on new product innovations for their company. Commercial systems like HAPS from Synopsys deliver better productivity because they offer superior design and debug automation for the hardware.
Consider this example of hardware/software integration that is very difficult, arguably impossible to replicate with a custom board.
Dense signal interconnect of a large SoC design may require thousands of signals to interconnect FPGAs. These can easily exceed the number of connections available between FPGAs. To resolve this you face two options: You can either partition the design into smaller blocks and spread it across more FPGAs to avoid pin overflows; or you can time multiplex the pins. With Synopsys ProtoCompiler, a partition solution can be generated, often in a matter of minutes, to assess the multiplexing demand. From there the engineer can decide whether to budget more FPGA resources or continue with the current FPGA count and rely on time division multiplexing (TDM) to solve pin congestion. The system automatically incorporates low-voltage differential signaling (LVDS) TDM circuits with optional real-time data integrity checks based on the partition result.
Because of the electromechanical characterization of the PCB layout, connector, and interconnect hardware, the resulting product will be far more reliable than one built by hand. HAPS system bring-up utilities communicate with the live hardware, and this helps ensure that TDM links are stable and train properly and, that during execution of the DUT, they can be monitored for data integrity. This is one example of the efficient integrated design of hardware, firmware and software for a commercial system.
More standalone use-cases for FPGA-based prototyping
The FPGA-based prototyping market has its foundations in validation of the functionality of an ASIC’s RTL before first silicon. This remains the primary use-case. But as designs have evolved to incorporate such elements as external IP, closer integration with embedded software and more, the technique has extended its reach in step.
There are eight other examples of how companies are increasingly using FPGA-based prototyping systems such as HAPS in their own right. Here’s the full list (so far):
- In-system validation of your RTL;
- In-system test of algorithms and IP under internal development;
- In-system validation of external IP;
- Regression test for late-stage ECOs;
- In-system test of physical-layer software and drivers;
- Early app integration into embedded operating systems;
- In-system validation of software on a standalone target platforms;
- Early delivery of evaluation and software development platforms to partners; and
- Implementing a common company-wide verification and prototyping infrastructure for use across multiple projects.
Some of these tasks are often considered sufficiently important that multiple boards and tool licenses will be dedicated to each, with confidence that the ROI is there.
We don’t really need to ask why. Each of these growing options – plus the established validation of RTL – represents a fundamental task when it comes to getting a design completed in time to achieve maximum profitability.
But the growing application and flexibility of FPGA-based prototyping does not end there.
FPGA-based prototyping has historically been seen as a late-stage technique. It still has many uses in that context. But it can also now be leveraged to integrate functional blocks in various abstractions. For some teams, this is the fastest (in some cases the only) way to integrate an SoC prior to tape out.
Hybrid prototyping is an example where SystemC/TLM models are combined with RTL device controllers connected to analog PHYs. This allows a design team to run system-level definitions of the latest CPU architecture and new software functionality alongside already-verified RTL and embedded code to be reused that is hosted on a HAPS board.
On one side there are transaction-level models within a virtual prototype. On the other is your golden RTL connected to physical I/O.
The big advantages here are that there is less reliance on RTL, that real world interfaces can be integrated, and that the software team gets an earlier start on its development work, potentially slicing weeks off the project cycle.
Consider the real cost
As noted at the very beginning, commercial FPGA-based prototypes look significantly more expensive compared with the ‘simple’ cost of fabricating a PCB with an FPGA mounted on it. Indeed, the costs can seem daunting even as the features FPGA-based prototypes now offer look increasingly attractive.
Your real goal though is achieving your target ROI: how do you make your investment in FPGA-based prototyping pay for itself. It is a complex equation, one that can involve a significant number of wide-ranging variables.
So having set the scene as to why FPGA-based prototyping has become a more vital part of many a design team’s arsenal in getting that ASIC out the door, we need to look at how you can budget and thereby justify its introduction or greater use within your design flow.
In the next part of this series, we will review some of the key questions you need to ask yourself before embarking on any FPGA-based prototyping project, including some that address the long-standing tension between ‘buy’ and ‘build’.
We will also offer some basic principles worth embracing to make your project successful. And we will introduce an estimation tool Synopsys has developed to help you make the right choices.
About the author
Troy Scott is product marketing manager responsible for FPGA-based prototyping software tools at Synopsys. He has 20 years of experience in the EDA and semiconductor industries. His background includes HDL synthesis and simulation, SoC prototyping, and IP evaluation and marketing.