FinFET parasitics come under control

By Carey Robertson |  1 Comment  |  Posted: December 9, 2013
Topics/Categories: EDA - DFM, IC Implementation  |  Tags: , , , ,  | Organizations:

Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

The introduction of finFET processes marks the first time that the CMOS transistor has had to be considered as a truly three-dimensional (3D) device, with all the complexity and uncertainty that this entails. The uncertainty springs from the 3D nature of the device, especially the structure of the source-drain region, and how it interacts with its immediate surroundings, the local interconnect, and the contacts.

As a result, device modelling has had to improve rapidly. The BSIM Group of the UC Berkeley Device Group has developed a model, known as BSIM-CMG (common multi-gate), to represent the resistances and capacitances that exist within finFETs.

To help alleviate some of the anxiety in moving to finFET processes, the foundries have worked very hard to provide device and parasitic accuracy data, as well as preserve the use model employed for previous processes.

From here on out, however, things get complicated quite quickly. For example, we have BSIM-CMG as a common way of representing the design values of a finFET, but each foundry then adds or subtracts components to the standard model to more closely represent the parasitics surrounding it. This customization is driven by the need of the individual foundries to match silicon results with their respective device and parasitic models, and the EDA tools used to predict the silicon behavior.

Additionally, at these advanced process nodes, the foundries desire a much tighter correlation between their processes, the ‘gold’ models they have built for these processes using scientific field solvers, and the output of the extraction tools that EDA vendors develop and designers use in the field. At the 28nm node, foundries wanted commercial extraction tools to be within 5 to 10% of their gold models. For finFET processes, foundries are requiring a mean accuracy error within 2% of the gold model, and a three-sigma standard deviation of just 6 to 7%.

The most challenging task is accounting for the more complex, unintended interactions between the finFET and its surroundings. Modelling these geometries is certainly a 3D problem. The device itself is 3D, it is very close to tall contacts, local interconnect has different heights, and it is surrounded above by a grid of complex metal interconnect. To do a good job of extracting parasitics around finFETs, we can’t keep working in two dimensions, or rely on 2.5D techniques such as table- or rule-based approaches. We must leverage 3D extraction technology around Front End of Line (FEOL) geometries.

Introducing field solvers is an important part of meeting the foundries’ requirements for better correlation between our extractors and foundry golden results. It also means that designers will have access to field solver results, which, until now, were primarily used for process characterization, not design. However, the use model for designers when performing parasitic extraction won’t change, because the tools will automatically move between field-solver and heuristics-based approaches.

How can we do this? First, we need high performance field solver technologies. Traditionally, field solvers were impractical for production usage, because they were too expensive computationally. At Mentor, we developed the Calibre xACT 3D extraction tool to address this issue. Calibre xACT 3D has proven to be an order of magnitude faster or more by employing adaptive gridding techniques to speed up the computation. It also has a highly-scalable architecture to take advantage of multiple CPU’s in modern compute environments. With these features, the Calibre xACT-3D tool can comfortably perform a field solver computation solution on designs ranging from small cells to large blocks incorporating several million transistors on a 32-CPU machine.

However, at the full-chip level, we need to consider multi-billion transistor designs, with tens of millions of nets at the top level. Therefore, fast field solvers alone will not be practical from a turnaround time perspective. Intelligent techniques and heuristics must be used to leverage field solver techniques around complex structures, then switch to table-based methods for more regular geometries. Switching to table-based methods at higher-level routes is feasible, because modelling the electrical field in the wiring grid is similar to what was seen at previous nodes. In fact, the first generation of finFET processes integrates finFET devices with the 20nm interconnect schemes that foundries used in their planar processes.

Lastly, when considering extraction of the top-level interconnect, we must provide more efficient computation methods. Naturally, device count and net count only increase, meaning the number of parasitics that must be calculated increases as well. Moreover, with double and multi-patterning playing an increasing role in manufacturing starting with the 20nm node, we are also experiencing a big jump in the number of interconnect corners. At 28nm, five interconnect corners are likely, but at 16nm, we see 11-15 corners. The traditional approach to increased computational requirements is to use more CPUs and improve the scalability of core algorithms. This is being done, but we are also implementing advanced multi-corner analysis schemes to enable more efficient computation. We used to estimate that each additional corner would incur 1X additional run time vs. a single corner. Now, we can process corners in parallel, to the point where each additional corner adds only 10% to overall turnaround time. This means that 15 corners now only require 2.5X the run time of a single corner. By leveraging additional CPUs with advanced multi-corner analysis, we can give designers equivalent (or better) turnaround times than they experienced at 28nm or 20nm.

The recent, rapid shift towards finFET processes has challenged the EDA industry to come up with effective solutions to complex new issues really quickly. At this time, the only real data we have is coming from test chips and other characterization vehicles. However, the data we are seeing show that the tools are accurately predicting silicon behavior. There is more work to do, but the good news is that EDA companies are collaborating with foundry teams to ease the anxiety and reduce the number of unknowns in switching to finFET processes. Arguably, we have more correlation data now between EDA tools and foundry silicon for finFET processes than we have had at similar points in the past for previous processes.

 

Author

Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products. He has been with Mentor Graphics for nine years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp,, working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley. He may be contacted at carey_robertson@mentor.com.

Company info

Mentor Graphics Corporation 
8005 SW Boeckman Road
Wilsonville, OR 97070
Phone: 800-592-2210 or 503-685-7000
www.mentor.com

 

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One Response to FinFET parasitics come under control

  1. Pingback: FinFET Fever…or FinFET Fear? « Foundry Solutions

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