The new landscape of advanced design

By Mark Bollar |  No Comments  |  Posted: February 11, 2014
Topics/Categories: EDA - IC Implementation  |  Tags: , , , , , , ,  | Organizations:

Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

In the last post, I argued that advanced design techniques are now being applied at established process nodes, such as 130nm, as well as those that are just emerging into commercial production, such as 20nm and 16nm. But which nodes are seeing the most design starts? Counter-intuitively, it’s not those at the leading edge.

Even though we read about 20nm, 16nm, and 10nm designs in the press all the time, and rarely hear a story leading with “New 90nm Design Development …” we know that new processes always follow the same pattern:  development, ramp-up, maturation, decline and obsolescence. What we forget is the typical product life cycle curve. Figure 1 shows the lifecycle curves for different process nodes over the past 13 years.

Design Starts per Year (Source: IBS Dec 2012)

Figure 1 Design Starts per Year (Source: IBS Dec 2012)

Design starts in 0.35um+, 0.35um, and 0.25um processes are now all in decline. Processes from 0.18um down to 90nm show a rise to maturity and then a gradual decline. Processes from 65nm down to 32/28nm are still in a ramp up to maturation. Finally, 22/20nm and 16/14nm are in the very early adoption phase.

The same data, looked at another way, shows more clearly where we are today. Figure 2 highlights design starts in 2013.

Design starts for 2013 (Source: IBS Dec 2012)

Figure 2 Design starts for 2013 (Source: IBS Dec 2012)

The graph shows the contribution of each process node towards total production.

Notice that the 180nm, 130nm and 65nm nodes are the three largest contributors. This is because they are used to make most of today’s everyday devices.

Take automobile electronics as a very visible example of a widely used class of devices that has different requirements from the microprocessors and graphics engines made on emerging process nodes. Key drivers for devices in this market include cost, reliability, robustness in harsh environments, high-voltage and ultra-low power utilization – not just pure processing power.

Until recently, this has been the reality. Everyday devices are made on established nodes, while graphics and CPU processors are made on emerging nodes. But recently, a disruption to Moore’s Law has changed the game for a growing number of chip companies.

Traditionally, Moore’s Law yielded performance and cost savings hand-in-hand, node-by-node, as shown in figure 3.

Gate cost per node (Source: IBS 2012)

Figure 3 Gate cost per node (Source: IBS 2012)

Costs fell steadily until the 20nm node, when the need to use double-patterning lithography to sustain the improvements in device density expected with the introduction of a new node pushed up manufacturing costs.

Faced with higher costs, some companies that have traditionally moved their designs to emerging processes as soon as possible have jumped off the train at 20nm.

For some product niches, there is little to worry about here because there are plenty of process nodes ahead before they get to 20nm. But companies with a diverse product portfolio have to manufacture at many process nodes, and will eventually have to deal with the additional cost and complexity of sub-20nm processes.

As a result of the disruption of the cost-improvement curve, industry analysts are already predicting that the 65nm node will have an extremely long life, and that the 45nm and 32/28nm nodes may follow suit.

Fortunately, technology exists to support both those who stick at 20nm-and-above process nodes, and those who venture below 20nm. Even better, companies designing with the market-leading place and route product, Synopsys’ IC Compiler, won’t have to seek out new tools. IC Compiler already enables advanced design at both established and emerging process nodes, with many of the techniques and strategies that have been developed to enable emerging node designs also applying to advanced designs on established process nodes.

Stepping back from the detail for a moment, the combination of growing markets for devices on established nodes, the application of advanced design techniques at both emerging and established process nodes, and the availability of tools and flows to support advanced design independent of process node, should broaden the scope of innovation in IC design. It’s going to be an interesting trend to watch play out.

Company info

Synopsys Corporate Headquarters
700 East Middlefield Road
Mountain View, CA 94043
(650) 584-5000
(800) 541-7737

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