EUV nears last-chance saloon
If you were to dramatize the situation for extreme ultraviolet (EUV) as the next-generation lithography technology for chipmaking as a movie, it would by now be in the difficult third act. Having been through many ups and downs, it’s now lying on a hospital bed and it’s not clear whether the slowing pulse will flatline or the patient will suddenly wake up, jump out of bed and save the day. Unfortunately for the technology, a Hollywood ending is looking unlikely. Its prognosis worsened considerably during the two-hour duration of a panel at the recent VLSI Technology Symposium that sought to find out which way lithography is going to go.
As the panelists talked about the Shakesperian nature of the panel’s title “To EUV or not EUV?”, a member of the audience joked: “It’s a tragedy and a comedy.”
It’s fairly easy to summarize the panel in a way that favors EUV: when throughput and operating costs reaches the right point, chipmakers will use it. The heavy investments by Intel and now TSMC in ASML may help stop EUV flatlining and point to a strong desire to get the technology on track. But that hope hides a harsh reality for a technology that has soaked up millions (possibly billions) of dollars of R&D investment. The panel experts reinforced the notion that multiple patterning is here. And it’s here to stay; get used to it. And the chances are that, within a couple of generations, just about everyone will be using self-aligned multiple patterning rather than the conceptually simpler litho-etch, litho-etch (LELE) form.
Unless its throughput increases dramatically through a massive increase in laser power – and this is something that has been promised but failed to materialize for a decade or more – EUV may just wind up being the machine that exposes contacts and cut masks – to render useful circuit features out of diffraction gratings – that are tough to handle using 193nm immersion equipment. But, despite being reasonably well suited to the task, EUV will face tougher competition in that scenario from clusters of slower, but smaller, cheaper and more energy-efficient e-beam direct-write machines.
Intel director of lithography Yan Borodovsky, who shared the Cledo Brunetti award with colleage Sam Sivakumar earlier in the day for contributions to the technology, argued that pitch splitting – Intel’s approach to self-aligned double patterning – based on 193nm immersion could work to 10nm and beyond. How? Simply split the pitch an increasing number of times. As Intel has already moved wholesale to 1D layout for critical layers, Borodovsky saw no problem in continuing the process, at least for the regular grid layout.
Doing the cuts and contacts presents greater challenges but this is where Borodovsky has argued for several years for the approach he calls complementary lithography. Use regular optical lithography for the grids and something else that is good at doing ‘random’ features for those tricky features. However, it became clear than Intel has moved from seeing EUV as essential for 14nm to being an option that’s worth exploring if ASML can hit its power and reliability milestones. Even at 7nm, with the exception of ASML’s technology center director Alek Chen, the panel was doubtful as to whether EUV would be production-ready. The good news is that, other that making life tougher from a design perspective, that delay would not affect scaling in a meaningful way.
Harry Levinson, senior fellow and manager of strategic litho at GlobalFoundries, said it won’t be essential to move to 1D layouts to make use of self-aligned double patterning (SADP). And it is likely to beat LELE because, as he noted, a number of panelists pointed out that overlay control is going to be very tough to achieve with any multiple patterning technique. So, something that offers self alignment – and it’s worked beautifully for CMOS gates and finFETs so far – has a natural advantage although it puts more pressure on design tools and potentially on production cost.
At this stage, LELE represents fewer problems in terms of design and does not suffer from some of the lithographic issues that SADP has at the moment. Over time, the overlay issues are likely to come to the fore and force a migration towards 1D design rules for the wider IC-design base. And, if these are in place by the time EUV moves into production, that is not a situation that favors the exclusive use of the technology in the critical layers. It will be, as Borodovsky pointed out, a mix-and-match situation.
