International Test Conference 2011 Anaheim. Day One.

By Paul Dempsey |  No Comments  |  Posted: September 20, 2011
Topics/Categories: no topics assigned  |  Tags:

The 2011 International Test Conference opened last night at Disneyland’s Convention Center in Anaheim with a panel that looked to get some idea of the shape of test in a decade’s time.

We’ll take a more detailed view of what was said in a full round-up from the conference in the next print edition of TDF, but here is one particularly striking takeaway.

Only so much could be said about what that future will look like. Even in the short-term, many of the test techniques being used – and the panel featured major users Intel, Qualcomm, Cisco Systems and IBM as well as vendor Mentor Graphics – are still what several panelists called ‘secret sauce’.

You can define many of the common problems facing the industry with relative ease. There are the proliferation of IO standards and the consequences of 3D which brings the inherent trickiness of taking die that are backgrinded and therefore otherwise altered in terms of their reliability and various properties. Then, there is the ongoing debate over the needed balance between functional and structural test.

And, as panelist Octavio Martinez, senior director of engineering with Qualcomm, noted, “Yield is king.”

But following through that thought Martinez also noted that his company sticks to a strict budget of test costs at a ceiling 5% of average unit cost, applied across a company with a run-rate of 3 million units a day.

That kind of constraint will not go away. Indeed Martinez added that we need a “Moore’s Law for Test”. “As the cost of silicon continues to go to next to nothing, especially at the transistor level, the cost of test needs to match that. Otherwise, we are going to be in deep, deep trouble.”

So, boost yield and you also get the chance to increase your test budget, but to get to that point and address the many problems emerging today – and with Qualcomm’s highly integrated devices, it’s not only dealing with the problems above but also the perennial thorny field of analog and mixed-signal test – you do undertake a massive amount of internal work. And it may not be in your interest to share all the fruits of that too soon for perfectly good commercial reasons.

Nevertheless, you can take a strategic view now. Janusz Rajski, director of engineering at Mentor Graphics and one of the fathers of TestKompress, said that the structure of test will need to center on a “block-based design approach” that is very portable, embedded and hierarchical”.

The next few days should take us further into these kinds of debate.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors