FastSPICE simulators hit their expiration date

By Bruce McGaughy |  No Comments  |  Posted: October 28, 2015
Topics/Categories: EDA - Verification  |  Tags: , ,  | Organizations:

Bruce McGaughy, CTO, ProPlus Design SolutionsDr Bruce McGaughy is CTO and senior vice president of engineering at ProPlus Design Solutions. He was most recently the chief architect of the simulation division and distinguished engineer at Cadence Design Systems.

Walk into any kitchen anywhere and you’ll see a cupboard or rack filled with spices, all of which have expiration dates. SPICE or FastSPICE simulators do as well and they are hitting their expiration dates right now, driven by the new requirements of finFET technology.

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. The FastSPICE simulator provides a good combination of capacity and speed but it trades those characteristics against accuracy and reliability. Full SPICE is computationally intensive, so it often makes sense to use the approximations provided by a FastSPICE engine but this comes at the cost of reducing the confidence designers have in their simulation results, which is problematic in the age of finFETs when the complex electrical environment they bring demands high accuracy.

As an example, Kirchoff’s current law (KCL) regularly breaks in FastSPICE simulations because they are not strictly converging the Newton Raphson iterations. That means designers will not be able to trace all signals. Some get lost, namely, those small, but important currents critical for advanced low-power designs that are seen as crucial to the success of finFET-based products. Unrelated to KCL, but also problematic causing accuracy and reliability problems, are the simplified device models and table models used in FastSPICE.

Simulation tradeoffs

Memory designers are used to making tradeoffs between accuracy and performance with their FastSPICE simulator. The regular nature of their designs provides opportunities to fine-tune options and settings for each circuit type in the knowledge that this will yield runtime savings on large arrays. But such in-depth tuning is impractical and not necessarily accurate for advanced designs, particularly circuits using finFET technology. Furthermore, a set of options that were tweaked for one design may be completely inaccurate for another design, or even at different process corners.

An unreliable simulator with inaccurate results used for verification and signoff could be disastrous as technology shrinks, supply voltages are reduced and process variations increase. This could lead to design respins, a huge waste of R&D effort and expensive fabrication costs.

Things need to change. We can call them giga-scale SPICE simulators, or “GigaSpice” for short. Rather than use approximations, the GigaSpice engine leverages advanced parallelization technology with interfaces that enable a drop-in replacement of FastSPICE in existing design flows. Because they use parallelism to accelerate a full SPICE solver, this type of engine removes the accuracy concerns and the efforts needed by designers to tune the simulator’s runtime options. GigaSpice simulators always converge and obey KCL, and accordingly offer the most accurate simulation results. This gives designers the confidence they need to handle large, giga-scale circuit simulation at leading-edge technologies.

GigaSpice offers the speed and capacity of FastSPICE, without compromising accuracy, making it the best option to replace FastSPICE when it comes to meeting emerging design challenges. That is why I believe Giga-scale SPICE simulators will become the golden reference and natural replacement for FastSPICE, and find its way into each circuit designer’s SPICE rack.

Comments are closed.


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors