September 2006

September 1, 2006

A top-level verification methodology including power supply and signal check using mixed-signal simulation

The ‘state-of-the-art’ solution for wireless transceiver RF ICs is single chip CMOS, integrating digital, analog, and RF blocks on a single chip. The architectures involved require new and challenging approaches to verification. To understand these, we first need to look back at the history of the transceiver architectures used for wireless mobile phone implementations during […]

Article  |  Tags:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors