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October 3, 2016
How place and route is adapting to challenges below 10nm
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
Article | Topics:
EDA - DFM
,
- EDA Topics
,
EDA - IC Implementation
| Tags:
cell pin access
,
double patterning
,
finFET
,
layout
,
minimum jog
,
multi-patterning
,
oxide diffusion
,
physical design
,
pin to track
,
place and route
,
submetal shape
| Organizations:
Mentor Graphics
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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