Accelerating PCIe verification

By Paul Graykowski |  No Comments  |  Posted: April 6, 2016
Topics/Categories: EDA - Verification  |  Tags: , , ,  | Organizations:

Paul Graykowski, senior manager at Synopsys responsible for PCIe verification IPPaul Graykowski is a senior manager at Synopsys responsible for PCIe verification IP. He has been with Synopsys for 16 years, focusing on verification technologies and methodologies. His interests include verification IP, UVM, verification methodology, and coverage.

PCI Express (PCIe) has been around for more than a decade, during which time it has been constantly revised and updated to offer more facilities and greater data transfer rates. The latest version, PCIe 4.0, announced in November 2011 and currently working its way through the standardization process, will support an interconnect bandwidth of 16Gbit/s, compared with the 2Gbit/s of the 1.0 specification.

Who needs this kind of speed? Synopsys has been delivering PCIe IP and verification IP (VIP) for years, and among our customer base, we find three types of users, some of whom are already pushing for early access to PCIe 4.0.

Three customers for faster PCIe

The first group is companies that build enterprise equipment, such as low-power servers, SSDs using the NVMe overlay to the PCIe standard, and data-protection solutions. These customers now see PCIe 3.0 at 8Gbit/s as part of the mainstream of their design practice, and want to use faster PCIe interconnect as soon as it is available.

The second group is the mobile sector, which is currently shifting from PCIe 2.0 to PCIe 3.0, and, as you would expect, focusing on low power. The third group is working on consumer applications, where they are focused very strongly on both cost and power reduction.

The good news for those who are committed to PCIe for the foreseeable future is that the transition from the 3.0 to 4.0 standard should be fairly straightforward. The 4.0 standard will be backwards compatible with prior generations, using the same connector pin-out, perhaps with some design changes to improve signaling while preserving backwards compatibility for plug-in cards. The signaling rate for 4.0 will be twice that of 3.0, at 16Gtransfer/s, and there won’t be any changes to the signal encoding. There aren’t expected to be major changes to the PIPE (physical interface for PCIe) spec, either.

Synopsys announced support for PCIe 4.0 in June 2014, offering a combination of controller, PHY and VIP, and has been working to keep these in line with the 0.x revisions of the 4.0 standard as they emerge. The controller IP has been designed to minimize the latency, gate-count and power consumption of 4.0 implementations. The PHY IP will offer equalization capabilities to increase signal integrity at high data rates across legacy channels, and the VIP is designed to make it easier to develop testbenches to exercise and validate PCIe implementations.

The 4.0 solution will sit alongside Synopsys’ existing offerings, which go all the way back to PCIe 1.0. These include configurable PCIe controllers supporting all port types in multiple lane widths, silicon-proven PHYs for processes ranging from 130nm to 14nm, and VIP written natively in SystemVerilog, with features such as automated error injections and source code for UVM-based test suites.

PCI e VIP - make vs buy

Why would you want to use any of these, especially the VIP, instead of developing your own? One good reason is because of the complexity of the PCIe specification, which currently stands at around 1000 pages and is evolving constantly. Simply keeping up to date with all the changes in the standard from version to version is, in itself, becoming a very large task.

The increasing complexity of the PCIe protocols, and the addition of new protocols that layer over those that are already established, is also leading to an exponential increase in the scale and complexity of the verification challenge. This is within the wider context of increasing design complexity, especially at the SoC level.

Synopsys PCIe VIP has been developed to help address these issues. It is written natively in SystemVerilog, so that it can be easily integrated into simulation environments without the need for PLIs or proprietary languages. And it has been optimized to work with VCS, for fast compilation and run times. The VIP is also designed to work with our Verdi debugger, which has been given an understanding of the PCI protocols so that it can present verification results both as signals and as high-level representations of each signal’s role in a particular protocol interaction.

Synopsys PCIe VIP also comes with a set of test suites, delivered in source code form, that can help design teams speed up their verification. To develop the test suites, we started with the PCIe spec, worked out what needed testing, and then wrote tests to achieve that. The resultant test suite and test plan form part of the VIP we deliver. The fact that the tests are derived directly from the spec means that if you are working with a new core or a new vendor, you can use the tests as a way to get some early confidence in the new blocks with which you’re working.

The VIP gives users access to all layers of the PCIe protocol stack - application, transaction, link, and PHY – and checks packets as they traverse these layers.

Other features include rich configurability options, built-in applications to simplify test development, the ability to configure error injection schemes and apply them to particular transactions, and much more. The VIP also supports the NVMe protocol, which is layered on top of PCIe and used for accessing storage systems such as SSDs.

On the debug front, the fact that the VIP is written in SystemVerilog makes it easier to access key internal signals for viewing in Verdi. This understands the PCIe protocols, and so can present the results in a graphical form that illustrates the protocol exchanges, with links to the underlying waveforms.

The Synopsys PCIe VIP suite offers a host of other features, which are detailed at the links below. The ‘make vs buy’ question remains. I look at this as follows. Users fall into two broad categories: those who need to implement the latest version of PCIe in order to have a differentiating advantage in their market; and those who need to implement it to remain competitive in a market that is already adopting it. The first group needs all the help it can get to implement the standard as quickly as possible, and crucially, for the implementation to be right first time. The second group, for whom a PCIe implementation represents a cost of market entry, needs to focus its engineering resources on the differentiating aspects of their design.

If you accept this analysis, then in both cases, buy comes out ahead of make.

Further info 

For a webinar including a demo of Synopsys PCIe VIP in action, click here.


Paul Graykowski is a senior manager at Synopsys responsible for PCIe verification IP. He has been with Synopsys for 16 years, focusing on verification technologies and methodologies. His interests include verification IP, UVM, verification methodology, and coverage.


Comments are closed.


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors