Volume 2

June 1, 2005

A methodology of integrated post tape-out flow for fast design to mask TAT

Semiconductor devices are being fabricated with features that are less than half the wavelength of the available lithography exposure tools. Increasing circuit density has improved the complexity and performance of ICs but also led to serious patterning proximity effects. These effects make the chips almost impossible to fabricate without optical proximity correction (OPC) technology. Thus, […]

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June 1, 2005

Formal verification poised for rapid growth

Design teams are becoming increasingly concerned at the growing disparity between the capacity of silicon in the latest processes and the design and verification capabilities of simulation tools. A number of trends are now converging to enable a step function increase in verification to complement and extend the debug and verification capabilities of HDL simulators. […]

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