clock domain crossing (CDC)

Today’s system-on-chip designs often need to encompass multiple asynchronous clocks. This raises the problem of verification for the resultant clock domain crossings. It is becoming apparent that functional simulation alone is not up to the task. Instead, engineers need to consider hybrid methodologies, combining structural and functional verification approaches. The use of assertions is also […]

Clock domain crossing (CDC) errors can cause serious design failures. These can be avoided by following a few critical guidelines and using well-established verification techniques. The guidelines include: When passing 1bit between clock domains: register the signal in the sending clock domain to remove combinational settling; and synchronize the signal into the receiving clock domain. […]