June 2005

June 1, 2005

SystemVerilog is changing everything

Considering how complexity has grown over the last 20 years, it is amazing how few dramatic shifts in the design and verification methodology have occurred. When they do happen — mylar to layout tools, gates to RTL, hand-crafted test vectors to testbench automation — they make our work as engineers easier and enable us to […]

Article  |  Tags:


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors