IP Topics

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  Debugging complex RISC-V processors

  RISC-V adoption is growing fast as is the ecosystem around the open-source core. Hardware and software are now vital for appropriate debug.

  Topics/Categories: IP - Assembly & Integration, EDA - Verification
  

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  Formal verification for SystemC/C++ designs

  Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.

  Topics/Categories: IP - Assembly & Integration, EDA - Verification
  

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  How to use runtime monitoring for automotive functional safety

  The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.

  Topics/Categories: Embedded - Architecture & Design, IP - Assembly & Integration, EDA - Verification
  

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  Introduction to the Compute Express Link (CXL) protocols

  A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.

  Topics/Categories: Embedded - Architecture & Design, IP - Selection
  

Assembly & Integration

1. Article Debugging complex RISC-V processors
2. Article Formal verification for SystemC/C++ designs
3. Article Resolving IP cell-name conflicts peacefully

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Design Management

1. Expert Insight Improved power management and faster time to market?
2. Expert Insight How to migrate SoC design to the cloud
3. Expert Insight Give the people what they want: toward making 3D IC mainstream

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Selection

1. Guide NAND flash
2. Article Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
3. Article Introduction to the Compute Express Link (CXL) device types

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