March 1, 2006
For years, ASIC and FPGA designers have shared the goal of having totally reusable intellectual property (IP) blocks. This goal has been partially fulfilled, with the introduction of high-level hardware description languages such as VHDL and Verilog, and powerful Register Transfer Level (RTL) synthesis tools in the late 1980s and early 1990s. However, with a […]
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December 1, 2005
No one disputes the promise inherent in the concept of design reuse. But the true value of what has been delivered so far is often debated. This paper proposes a reuse methodology that is both practical and real and which uses behavioral synthesis as its driving technology. It discusses the most basic elements of behavioral […]
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June 1, 2005
The network-on-chip (NoC) design paradigm is seen as a way of enabling the integration of an exceedingly high number of computational and storage blocks in a single chip. But its adoption and practical implementation face important and unsolved issues related to design methodologies, test strategies, and dedicated CAD tools. The System-on-a-Chip Research Lab at the […]
June 1, 2005
Alcatel Space supplies complete satellites for use in geostationary and low-earth orbit as well as custom designs for specific missions. These are based on various in-house platforms which support different payloads according to their final use. Fields serviced include telecommunications, observation, meteorology, navigation and science. The company has 5,600 employees, of which around 2,000 work […]
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